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7c1f8ce395
Add initial support for the PHYTEC phyBOARD-Segin-i.MX93 board based on the PHYTEC phyCORE-i.MX93 SoM. Supported features: - 1GB LPDDR4 RAM - eMMC - external SD - FEC Ethernet - debug UART - watchdog Signed-off-by: Mathieu Othacehe <othacehe@gnu.org> Tested-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Yannic Moog <y.moog@phytec.de>
126 lines
2.9 KiB
Text
126 lines
2.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 PHYTEC Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>, Christoph Stoidner <c.stoidner@phytec.de>
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* Copyright (C) 2024 Mathieu Othacehe <m.othacehe@gmail.com>
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*
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* Product homepage:
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* https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
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*/
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#include <dt-bindings/leds/common.h>
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#include "imx93.dtsi"
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/{
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model = "PHYTEC phyCORE-i.MX93";
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compatible = "phytec,imx93-phycore-som", "fsl,imx93";
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reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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alloc-ranges = <0 0x80000000 0 0x40000000>;
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size = <0 0x10000000>;
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linux,cma-default;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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led-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_HEARTBEAT;
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gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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/* Ethernet */
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
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<&clk IMX93_CLK_ENET_REF>,
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<&clk IMX93_CLK_ENET_REF_PHY>;
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assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
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<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
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<&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
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assigned-clock-rates = <100000000>, <50000000>, <50000000>;
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status = "okay";
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mdio: mdio {
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clock-frequency = <5000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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/* Watchdog */
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&wdog3 {
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
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MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
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MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
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MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
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MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
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MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
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MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
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MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
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MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
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>;
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};
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pinctrl_leds: ledsgrp {
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fsl,pins = <
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MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x1386
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x1386
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
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>;
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};
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};
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