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The x250 and SE250 are series of 10G L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
274 lines
4.6 KiB
Text
274 lines
4.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Allied Telesis Labs
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*/
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#include "cn9130.dtsi"
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/ {
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model = "Allied Telesis x250";
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compatible = "alliedtelesis,x250",
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"marvell,cn9130",
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"marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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aliases {
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serial0 = &uart0;
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i2c0 = &cp0_i2c0;
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i2c1 = &cp0_i2c1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-leds {
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compatible = "gpio-leds";
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fault {
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label = "fault:red";
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gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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};
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};
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/*
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* AP related configuration
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*/
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&ap_pinctl {
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/* AP_MPP Pins:
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* GPIO & NC [0-6,9-10,12]
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* UART0 [11,19]
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* UART1 [7,8]
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* Note: The x250-28XTm PT1 units has the console port wired
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* to the second uart pins (UART1). This was fixed in all
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* subsequent models.
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* Here we choose to configure the pin control for both
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* uarts to cater for either unit.
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0 0 0 0 0 0 0 3 3 0
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0 3 0 0 0 0 0 0 0 3 >;
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};
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&ap_gpio0 {
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pp-reset {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "pp-reset";
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};
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};
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/*
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* CP related configuration
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*/
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&cp0_pinctl {
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/* MPP Bus:
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* [0-1] DEV
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* [2-8] GPIO
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* [9] DEV
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* [10-12] GPIO
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* [13] ND_RB
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* [14] GPIO
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* [15-28] DEV
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* [29-30] GPIO
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* [31] DEV
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* [32-34] GPIO
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* [35-36] I2C1
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* [37-38] I2C0
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* [39-55] GPIO
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* [56-60] SPI
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* [61-62] GPIO
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 0 0 0 0 0 0 0 1
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0 0 0 2 0 1 1 1 1 1
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1 1 1 1 1 1 1 1 1 0
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0 1 0 0 0 2 2 2 2 0
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0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 6 6 6 6
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6 0 0>;
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = <37 38>;
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marvell,function = <2>;
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};
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cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 {
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marvell,pins = <37 38>;
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marvell,function = <0>;
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = <35 36>;
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marvell,function = <2>;
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};
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cp0_nand_pins: cp0-nand-pins {
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marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>;
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marvell,function = <1>;
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};
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cp0_nand_rb: cp0-nand-rb {
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marvell,pins = <13>;
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marvell,function = <2>;
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = <56 57 58 59 60>;
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marvell,function = <6>;
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};
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};
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&cp0_comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_IGNORE>;
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};
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};
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&cp0_pcie0 {
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num-lanes = <1>;
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/* non-prefetchable memory */
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ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
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status = "disabled";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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clock-frequency = <200000000>;
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};
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&cp0_utmi0 {
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status = "okay";
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};
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&cp0_usb3_0 {
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status = "okay";
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};
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&cp0_spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi0_pins>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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};
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};
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&cp0_nand {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-timing-mode = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@user {
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reg = <0x00000000 0x10000000>;
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label = "user";
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};
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};
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};
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&cp0_gpio0
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{
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nand-protect {
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gpio-hog;
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gpios = <29 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "nand-protect";
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};
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};
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&cp0_gpio1
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{
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usb-en {
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gpio-hog;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-en";
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};
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phy-reset {
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gpio-hog;
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gpios = <21 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "phy-reset";
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};
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};
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&cp0_i2c0 {
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status = "okay";
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&cp0_i2c0_pins>;
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pinctrl-1 = <&cp0_i2c0_gpio_pins>;
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scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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mux@71 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9546";
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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rtc@68 {
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compatible = "adi,max31331";
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reg = <0x68>;
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};
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};
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};
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};
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&cp0_i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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};
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