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f10fc277dc
In OP-TEE, the "optee_core@" node is reserved, appended in non secure
device tree (see mark_tzdram_as_reserved() function under CFG_DT) so
this name must be checked in optee_get_reserved_memory().
We keep the check on /reserved-memory/optee@ node to have backward
compatibility with STMT32Image booting, when the reserved node is
already present in U-Boot or SPL device tree with name "optee@".
This patch solves a boot issue on board with OP-TEE for U-Boot
compiled with stm32mp15_defconfig and without secure configuration
device tree (stm32mp157c-dk2.dts for example).
Fixes: 5fe9e0deab ("stm32mp: allow calling optee_get_reserved_memory()
from U-Boot")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY LOGC_ARCH
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#include <dm.h>
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#include <efi_loader.h>
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#include <image.h>
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#include <init.h>
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#include <lmb.h>
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#include <log.h>
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#include <ram.h>
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#include <asm/global_data.h>
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#include <asm/system.h>
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#include <mach/stm32mp.h>
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DECLARE_GLOBAL_DATA_PTR;
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int optee_get_reserved_memory(u32 *start, u32 *size)
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{
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fdt_addr_t fdt_mem_size;
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fdt_addr_t fdt_start;
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ofnode node;
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node = ofnode_path("/reserved-memory/optee");
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if (!ofnode_valid(node)) {
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node = ofnode_path("/reserved-memory/optee_core");
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if (!ofnode_valid(node))
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return -ENOENT;
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}
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fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
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*start = fdt_start;
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*size = fdt_mem_size;
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return (fdt_start < 0) ? fdt_start : 0;
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}
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int dram_init(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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/* in case there is no RAM driver, retrieve DDR size from DT */
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if (ret == -ENODEV) {
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return fdtdec_setup_mem_size_base();
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} else if (ret) {
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log_err("RAM init failed: %d\n", ret);
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return ret;
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}
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ret = ram_get_info(dev, &ram);
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if (ret) {
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log_debug("Cannot get RAM size: %d\n", ret);
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return ret;
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}
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log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
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gd->ram_size = ram.size;
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return 0;
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}
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phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
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{
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phys_size_t size;
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phys_addr_t reg;
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u32 optee_start, optee_size;
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if (!total_size)
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return gd->ram_top;
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/*
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* make sure U-Boot uses address space below 4GB boundaries even
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* if the effective available memory is bigger
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*/
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gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
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/* add 8M for U-Boot reserved memory: display, fdt, gd,... */
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size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
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reg = gd->ram_top - size;
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/* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */
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if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) {
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if (!optee_get_reserved_memory(&optee_start, &optee_size))
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reg = ALIGN(optee_start - size, MMU_SECTION_SIZE);
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}
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/* before relocation, mark the U-Boot memory as cacheable by default */
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if (!(gd->flags & GD_FLG_RELOC))
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mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
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return reg + size;
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}
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