u-boot/arch/riscv/cpu
Lukas Funke 19b762cf83 board: starfive: Rename spl_soc_init() to spl_dram_init()
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function actually does. Also
spl_dram_init() is commonly used for dram initialization and should be
called from board_init_f().

Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-05-02 00:01:18 +08:00
..
andesv5 riscv: andesv5: Set default cache line size to 64-bytes 2024-05-01 22:40:00 +08:00
cv1800b riscv: cache: Implement dcache for cv1800b 2024-04-09 11:30:02 +08:00
fu540 board: sifive: Rename spl_soc_init() to spl_dram_init() 2024-05-02 00:01:18 +08:00
fu740 board: sifive: Rename spl_soc_init() to spl_dram_init() 2024-05-02 00:01:18 +08:00
generic riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
jh7110 board: starfive: Rename spl_soc_init() to spl_dram_init() 2024-05-02 00:01:18 +08:00
cpu.c riscv: support extension probing using riscv, isa-extensions 2024-04-09 11:30:17 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Align the trap handler to 64 bytes 2023-11-02 15:15:46 +08:00
start.S riscv: add backtrace support 2024-04-09 11:29:38 +08:00
u-boot-spl.lds riscv: Update alignment for some sections in linker scripts 2023-04-20 20:45:08 +08:00
u-boot.lds riscv: Fix alignment of RELA sections in the linker scripts 2023-06-27 10:09:51 +08:00