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35638172f9
Initial creation of new system manager driver. Add supports for the SOCFPGA System Manager Register block which aggregates different peripheral function into one area. On 64 bit ARM parts, the system manager only can be accessed during EL3 mode, this driver model provide user the high level access to system register and abstract user from low level access. The base address of system manager can be retrieved using DT framework through the System Manager driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
192 lines
7.1 KiB
C
192 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*/
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#ifndef _SYSTEM_MANAGER_SOC64_H_
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#define _SYSTEM_MANAGER_SOC64_H_
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#include <linux/bitops.h>
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void sysmgr_pinmux_init(void);
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void populate_sysmgr_fpgaintf_module(void);
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void populate_sysmgr_pinmux(void);
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SYSMGR_SOC64_SILICONID_1 0x00
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#define SYSMGR_SOC64_SILICONID_2 0x04
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#define SYSMGR_SOC64_MPU_STATUS 0x10
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#define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc
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#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1
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#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34
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#define SYSMGR_SOC64_USB0_L3MASTER 0x38
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#define SYSMGR_SOC64_USB1_L3MASTER 0x3c
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#define SYSMGR_SOC64_DMAC0_L3_MASTER 0x74
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#define SYSMGR_SOC64_ETR_L3_MASTER 0x78
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#define SYSMGR_SOC64_DMAC1_L3_MASTER 0x7C
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#define SYSMGR_SOC64_SEC_CTRL_SLT 0x80
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#define SYSMGR_SOC64_OSC_TRIM 0x84
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#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG 0x88
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#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG 0x8C
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#define SYSMGR_SOC64_ECC_INTMASK_VALUE 0x90
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#define SYSMGR_SOC64_ECC_INTMASK_SET 0x94
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#define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98
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#define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C
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#define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0
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#define SYSMGR_SOC64_MPFE_CONFIG 0x228
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#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258
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#define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C
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#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(31, 0)
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#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29)
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#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT 29
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#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK BIT(27)
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#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK BIT(28)
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#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK GENMASK(28, 27)
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#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK BIT(1)
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#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK BIT(0)
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#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0)
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#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0)
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#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1)
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#else
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#define SYSMGR_SOC64_NAND_AXUSER 0x5c
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#define SYSMGR_SOC64_DMA_L3MASTER 0x74
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#define SYSMGR_SOC64_DDR_MODE 0xb8
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#else
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#define SYSMGR_SOC64_HMC_CLK 0xb4
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#define SYSMGR_SOC64_IO_PA_CTRL 0xb8
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#endif
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#define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0
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#define SYSMGR_SOC64_GPO 0xe4
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#define SYSMGR_SOC64_GPI 0xe8
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#define SYSMGR_SOC64_MPU 0xf0
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#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
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#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/
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#define SYSMGR_SOC64_DMA 0x20
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#define SYSMGR_SOC64_DMA_PERIPH 0x24
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#define SYSMGR_SOC64_WDDBG 0x08
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#define SYSMGR_SOC64_SDMMC 0x28
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#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2C
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#define SYSMGR_SOC64_FPGAINTF_EN1 0x68
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#define SYSMGR_SOC64_FPGAINTF_EN2 0x6C
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#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
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#define SYSMGR_SOC64_NOC_TIMEOUT 0xC0
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#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xC4
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#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xC8
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#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xCC
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#define SYSMGR_SOC64_NOC_IDLEACK 0xd0
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#define SYSMGR_SOC64_NOC_IDLESTATUS 0xD4
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#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xD8
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#define SYSMGR_SOC64_FPGA_CONFIG 0xDC
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#define SYSMGR_SOC64_TSN_GLOBAL 0x40
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#define SYSMGR_SOC64_TSN_0 0x44
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#define SYSMGR_SOC64_TSN_1 0x48
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#define SYSMGR_SOC64_TSN_2 0x4C
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#define SYSMGR_SOC64_TSN_0_ACE 0x50
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#define SYSMGR_SOC64_TSN_1_ACE 0x54
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#define SYSMGR_SOC64_TSN_2_ACE 0x58
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#define SYSMGR_SOC64_EMAC_GLOBAL SYSMGR_SOC64_TSN_GLOBAL
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#define SYSMGR_SOC64_EMAC0 SYSMGR_SOC64_TSN_0
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#define SYSMGR_SOC64_EMAC1 SYSMGR_SOC64_TSN_1
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#define SYSMGR_SOC64_EMAC2 SYSMGR_SOC64_TSN_2
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#define SYSMGR_SOC64_EMAC0_ACE SYSMGR_SOC64_TSN_0_ACE
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#define SYSMGR_SOC64_EMAC1_ACE SYSMGR_SOC64_TSN_1_ACE
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#define SYSMGR_SOC64_EMAC2_ACE SYSMGR_SOC64_TSN_2_ACE
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20C
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21C
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220
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#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224
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#define SYSMGR_SOC64_PINSEL0 0x1000
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#define SYSMGR_SOC64_IOCTRL0 0x1130
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#define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300
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#define SYSMGR_SOC64_EMAC1_USEFPGA 0x1304
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#define SYSMGR_SOC64_EMAC2_USEFPGA 0x1308
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#define SYSMGR_SOC64_I2C0_USEFPGA 0x130c
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#define SYSMGR_SOC64_I2C1_USEFPGA 0x1310
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#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA 0x1314
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#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA 0x1318
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#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA 0x131c
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#define SYSMGR_SOC64_NAND_USEFPGA 0x1320
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#define SYSMGR_SOC64_SPIM0_USEFPGA 0x1328
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#define SYSMGR_SOC64_SPIM1_USEFPGA 0x132c
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#define SYSMGR_SOC64_SPIS0_USEFPGA 0x1330
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#define SYSMGR_SOC64_SPIS1_USEFPGA 0x1334
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#define SYSMGR_SOC64_UART0_USEFPGA 0x1338
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#define SYSMGR_SOC64_UART1_USEFPGA 0x133c
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#define SYSMGR_SOC64_MDIO0_USEFPGA 0x1340
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#define SYSMGR_SOC64_MDIO1_USEFPGA 0x1344
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#define SYSMGR_SOC64_MDIO2_USEFPGA 0x1348
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#define SYSMGR_SOC64_JTAG_USEFPGA 0x1350
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#define SYSMGR_SOC64_SDMMC_USEFPGA 0x1354
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#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
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#define SYSMGR_SOC64_IODELAY0 0x1400
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/*
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* Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
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* Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
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* storing qspi ref clock (kHz)
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*/
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#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31)
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#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
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#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
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#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
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#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
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#define SYSMGR_ECC_OCRAM_EN BIT(0)
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#define SYSMGR_ECC_OCRAM_SERR BIT(3)
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#define SYSMGR_ECC_OCRAM_DERR BIT(4)
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#define SYSMGR_FPGACONFIG_FPGA_COMPLETE BIT(0)
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#define SYSMGR_FPGACONFIG_EARLY_USERMODE BIT(1)
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#define SYSMGR_FPGACONFIG_READY_MASK (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \
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SYSMGR_FPGACONFIG_EARLY_USERMODE)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_NAND BIT(4)
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#define SYSMGR_FPGAINTF_SDMMC BIT(8)
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#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
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#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
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#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
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#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
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#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
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/* EMAC Group Bit definitions */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
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#define SYSMGR_NOC_H2F_MSK 0x00000001
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#define SYSMGR_NOC_LWH2F_MSK 0x00000010
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#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
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#define SYSMGR_DMA_IRQ_NS 0xFF000000
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#define SYSMGR_DMA_MGR_NS 0x00010000
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#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
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#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0xFF0F0F0F
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#define SYSMGR_SOC64_DDR_MODE_MSK BIT(0)
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#endif
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#endif /* _SYSTEM_MANAGER_SOC64_H_ */
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