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9bb68bff4e
set/way instructions "dc cisw" which is used by the "dcache flush" command only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in cache coherency unit, hence this patch enables data flush from system memory cache of CCU into DDR memory. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
64 lines
2 KiB
C
64 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#include <wait_bit.h>
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#include <asm/arch/base_addr_soc64.h>
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#include <linux/bitfield.h>
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#define CCU_DMI0_DMIUSMCTCR SOCFPGA_CCU_ADDRESS + 0x7300
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#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_ADDRESS + 0x7340
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#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_ADDRESS + 0x7344
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#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0)
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#define MAX_DISTRIBUTED_MEM_INTERFACE 2
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#define FLUSH_ALL_ENTRIES 0x4
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#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16)
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#define ARRAY_ID_TAG 0x0
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#define ARRAY_ID_DATA 0x1
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#define CACHE_OPERATION_DONE BIT(0)
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#define TIMEOUT_200MS 200
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int __asm_flush_l3_dcache(void)
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{
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int i;
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int ret = 0;
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/* Flushing all entries in CCU system memory cache */
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for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
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/*
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* Skipping if the system memory cache is not enabled for
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* particular DMI
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*/
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if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000))))
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continue;
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writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
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FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
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(uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
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/* Wait for cache maintenance operation done */
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ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
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(i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
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false);
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if (ret) {
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debug("%s: Timeout while waiting for flushing tag in DMI%d done\n",
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__func__, i);
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return ret;
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}
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writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
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FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
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(uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
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/* Wait for cache maintenance operation done */
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ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
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(i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
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false);
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if (ret)
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debug("%s: Timeout waiting for flushing data in DMI%d done\n",
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__func__, i);
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}
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return ret;
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}
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