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3c65670cb6
The pca mux is not added to the i2c0 bus so remove it from the bus. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/3dfe8b41142de2e8c25c56702450ae1a6b1becc0.1704725223.git.michal.simek@amd.com
102 lines
2.1 KiB
Text
102 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP ZCU1285 RevA
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*
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* (C) Copyright 2018 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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/ {
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model = "ZynqMP ZCU1285 RevA";
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compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285",
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"xlnx,zynqmp";
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aliases {
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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mmc0 = &sdhci1;
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ethernet0 = &gem1; /* EMIO */
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i2c = &i2c0; /* EMIO */
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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&dcc {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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};
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&gem1 {
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */
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rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */
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txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */
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txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */
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rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */
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rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */
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rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */
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rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */
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rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */
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txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */
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txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */
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txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */
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txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */
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};
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};
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};
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&gpio {
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status = "okay";
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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};
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};
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&uart0 {
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status = "okay";
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};
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&sdhci1 {
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status = "okay";
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/*
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* This property should be removed for supporting UHS mode
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*/
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no-1-8-v;
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xlnx,mio-bank = <1>;
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};
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