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57c2a6364e
As was done in past for zcu102 append -hog to node name to pass dt-schema. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/112e36e2578c84f30c3c038440405069671d2853.1726219714.git.michal.simek@amd.com
80 lines
1.6 KiB
Text
80 lines
1.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3)
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*
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* (C) Copyright 2019 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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/plugin/;
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/{
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compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03";
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fragment@0 {
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target = <&dc_i2c>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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x_prc_eeprom: eeprom@52 { /* u1 */
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compatible = "atmel,24c02";
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reg = <0x52>;
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};
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x_prc_tca9534: gpio@22 { /* u3 tca9534 */
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compatible = "nxp,pca9534";
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reg = <0x22>;
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gpio-controller; /* IRQ not connected */
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#gpio-cells = <2>;
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gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
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"", "", "", "";
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gtr-sel0-hog {
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gpio-hog;
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gpios = <0 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_1";
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};
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gtr-sel1-hog {
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gpio-hog;
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gpios = <1 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_2";
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};
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gtr-sel2-hog {
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gpio-hog;
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gpios = <2 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_3";
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};
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gtr-sel3-hog {
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gpio-hog;
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gpios = <3 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_4";
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};
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};
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x_prc_si5338: clock-generator@70 { /* U9 */
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compatible = "silabs,si5338";
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reg = <0x70>; /* FIXME */
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};
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};
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};
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fragment@1 {
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target = <&i2c1>; /* Must be enabled via J90/J91 */
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom_versal: eeprom@51 { /* u2 */
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compatible = "atmel,24c02";
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reg = <0x51>;
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};
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};
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};
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};
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