mirror of
https://github.com/u-boot/u-boot.git
synced 2025-04-17 02:15:02 +00:00
70fc84493c
Sync the devicetree files from the official Linux kernel tree, v6.10. This is covering Allwinner SoCs with 32-bit and 64-bit ARM cores. Besides mostly cosmectic changes, this adds cpufreq support to H616 boards, Nothing that U-Boot needs for itself, but helpful to pass on to kernels. We also get the .dts files for the Tanix TX1 TV box and three Anbernic handheld gaming devices. As before, this omits the non-backwards compatible changes to the R_INTC controller, to remain compatible with older kernels. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
851 lines
21 KiB
Text
851 lines
21 KiB
Text
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun6i-rtc.h>
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#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
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#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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simplefb_lcd: framebuffer-lcd0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
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<&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
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<&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
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status = "disabled";
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};
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};
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de: display-engine {
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/* compatible gets set in SoC specific dtsi file */
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allwinner,pipelines = <&fe0>;
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status = "disabled";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,cpu-registers-not-fw-configured;
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};
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cpus {
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enable-method = "allwinner,sun8i-a23";
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-accuracy = <50000>;
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clock-output-names = "osc24M";
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};
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ext_osc32k: ext-osc32k-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-accuracy = <50000>;
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clock-output-names = "ext-osc32k";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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system-control@1c00000 {
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compatible = "allwinner,sun8i-a23-system-control";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c: sram@1d00000 {
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compatible = "mmio-sram";
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reg = <0x01d00000 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x01d00000 0x80000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun8i-a23-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x80000>;
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};
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};
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};
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dma: dma-controller@1c02000 {
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compatible = "allwinner,sun8i-a23-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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nfc: nand-controller@1c03000 {
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compatible = "allwinner,sun8i-a23-nand-controller";
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reg = <0x01c03000 0x1000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
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clock-names = "ahb", "mod";
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resets = <&ccu RST_BUS_NAND>;
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reset-names = "ahb";
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dmas = <&dma 5>;
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dma-names = "rxtx";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tcon0: lcd-controller@1c0c000 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma 12>;
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clocks = <&ccu CLK_BUS_LCD>,
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<&ccu CLK_LCD_CH0>,
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<&ccu 13>;
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clock-names = "ahb",
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"tcon-ch0",
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"lvds-alt";
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clock-output-names = "tcon-data-clock";
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#clock-cells = <0>;
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resets = <&ccu RST_BUS_LCD>,
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<&ccu RST_BUS_LVDS>;
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reset-names = "lcd",
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"lvds";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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reg = <0>;
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tcon0_in_drc0: endpoint {
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remote-endpoint = <&drc0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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reg = <1>;
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};
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};
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>,
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<&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>,
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<&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>,
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<&ccu CLK_MMC2>,
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<&ccu CLK_MMC2_OUTPUT>,
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<&ccu CLK_MMC2_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@1c19000 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c19000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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dr_mode = "otg";
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status = "disabled";
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};
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usbphy: phy@1c19400 {
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/*
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* compatible and address regions get set in
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* SoC specific dtsi file
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*/
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>;
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clock-names = "usb0_phy",
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"usb1_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset",
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"usb1_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@1c1a000 {
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compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI>;
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resets = <&ccu RST_BUS_EHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@1c1a400 {
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compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
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resets = <&ccu RST_BUS_OHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@1c20000 {
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c20800 0x400>;
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/* interrupts get set in SoC specific dtsi file */
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
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<&rtc CLK_OSC32K>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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i2c0_pins: i2c0-pins {
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pins = "PH2", "PH3";
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function = "i2c0";
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};
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i2c1_pins: i2c1-pins {
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pins = "PH4", "PH5";
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function = "i2c1";
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};
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i2c2_pins: i2c2-pins {
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pins = "PE12", "PE13";
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function = "i2c2";
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};
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lcd_rgb666_pins: lcd-rgb666-pins {
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pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
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"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
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"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
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"PD24", "PD25", "PD26", "PD27";
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function = "lcd0";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2",
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"PF3", "PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc1_pg_pins: mmc1-pg-pins {
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pins = "PG0", "PG1", "PG2",
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"PG3", "PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_8bit_pins: mmc2-8bit-pins {
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pins = "PC5", "PC6", "PC8",
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"PC9", "PC10", "PC11",
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"PC12", "PC13", "PC14",
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"PC15", "PC16";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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nand_pins: nand-pins {
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pins = "PC0", "PC1", "PC2", "PC5",
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"PC8", "PC9", "PC10", "PC11",
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"PC12", "PC13", "PC14", "PC15";
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function = "nand0";
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};
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nand_cs0_pin: nand-cs0-pin {
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pins = "PC4";
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function = "nand0";
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bias-pull-up;
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};
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nand_cs1_pin: nand-cs1-pin {
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pins = "PC3";
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function = "nand0";
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bias-pull-up;
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};
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nand_rb0_pin: nand-rb0-pin {
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pins = "PC6";
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function = "nand0";
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bias-pull-up;
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};
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nand_rb1_pin: nand-rb1-pin {
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pins = "PC7";
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function = "nand0";
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bias-pull-up;
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};
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pwm0_pin: pwm0-pin {
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pins = "PH0";
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function = "pwm0";
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};
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uart0_pf_pins: uart0-pf-pins {
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pins = "PF2", "PF4";
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function = "uart0";
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};
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uart1_pg_pins: uart1-pg-pins {
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pins = "PG6", "PG7";
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function = "uart1";
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};
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uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
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pins = "PG8", "PG9";
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function = "uart1";
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};
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};
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timer@1c20c00 {
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compatible = "allwinner,sun8i-a23-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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wdt0: watchdog@1c20ca0 {
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compatible = "allwinner,sun6i-a31-wdt";
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reg = <0x01c20ca0 0x20>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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pwm: pwm@1c21400 {
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compatible = "allwinner,sun7i-a20-pwm";
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reg = <0x01c21400 0xc>;
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clocks = <&osc24M>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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lradc: lradc@1c22800 {
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compatible = "allwinner,sun4i-a10-lradc-keys";
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reg = <0x01c22800 0x100>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart0: serial@1c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@1c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@1c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
|
resets = <&ccu RST_BUS_UART3>;
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@1c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART4>;
|
|
resets = <&ccu RST_BUS_UART4>;
|
|
dmas = <&dma 10>, <&dma 10>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@1c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
|
resets = <&ccu RST_BUS_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@1c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
|
resets = <&ccu RST_BUS_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mali: gpu@1c40000 {
|
|
compatible = "allwinner,sun8i-a23-mali",
|
|
"allwinner,sun7i-a20-mali", "arm,mali-400";
|
|
reg = <0x01c40000 0x10000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gp",
|
|
"gpmmu",
|
|
"pp0",
|
|
"ppmmu0",
|
|
"pp1",
|
|
"ppmmu1",
|
|
"pmu";
|
|
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
|
clock-names = "bus", "core";
|
|
resets = <&ccu RST_BUS_GPU>;
|
|
#cooling-cells = <2>;
|
|
|
|
assigned-clocks = <&ccu CLK_GPU>;
|
|
assigned-clock-rates = <384000000>;
|
|
};
|
|
|
|
gic: interrupt-controller@1c81000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x2000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
fe0: display-frontend@1e00000 {
|
|
/* compatible gets set in SoC specific dtsi file */
|
|
reg = <0x01e00000 0x20000>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
|
|
<&ccu CLK_DRAM_DE_FE>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_BUS_DE_FE>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fe0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
fe0_out_be0: endpoint {
|
|
remote-endpoint = <&be0_in_fe0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
be0: display-backend@1e60000 {
|
|
/* compatible gets set in SoC specific dtsi file */
|
|
reg = <0x01e60000 0x10000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
|
|
<&ccu CLK_DRAM_DE_BE>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_BUS_DE_BE>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
be0_in: port@0 {
|
|
reg = <0>;
|
|
|
|
be0_in_fe0: endpoint {
|
|
remote-endpoint = <&fe0_out_be0>;
|
|
};
|
|
};
|
|
|
|
be0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
be0_out_drc0: endpoint {
|
|
remote-endpoint = <&drc0_in_be0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
drc0: drc@1e70000 {
|
|
/* compatible gets set in SoC specific dtsi file */
|
|
reg = <0x01e70000 0x10000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
|
|
<&ccu CLK_DRAM_DRC>;
|
|
clock-names = "ahb", "mod", "ram";
|
|
resets = <&ccu RST_BUS_DRC>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
drc0_in: port@0 {
|
|
reg = <0>;
|
|
|
|
drc0_in_be0: endpoint {
|
|
remote-endpoint = <&be0_out_drc0>;
|
|
};
|
|
};
|
|
|
|
drc0_out: port@1 {
|
|
reg = <1>;
|
|
|
|
drc0_out_tcon0: endpoint {
|
|
remote-endpoint = <&tcon0_in_drc0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rtc: rtc@1f00000 {
|
|
compatible = "allwinner,sun8i-a23-rtc";
|
|
reg = <0x01f00000 0x400>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-output-names = "osc32k", "osc32k-out";
|
|
clocks = <&ext_osc32k>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
r_intc: interrupt-controller@1f00c00 {
|
|
compatible = "allwinner,sun6i-a31-r-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x01f00c00 0x400>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
prcm@1f01400 {
|
|
compatible = "allwinner,sun8i-a23-prcm";
|
|
reg = <0x01f01400 0x200>;
|
|
|
|
ar100: ar100-clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&osc24M>;
|
|
clock-output-names = "ar100";
|
|
};
|
|
|
|
ahb0: ahb0-clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&ar100>;
|
|
clock-output-names = "ahb0";
|
|
};
|
|
|
|
apb0: apb0-clk {
|
|
compatible = "allwinner,sun8i-a23-apb0-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&ahb0>;
|
|
clock-output-names = "apb0";
|
|
};
|
|
|
|
apb0_gates: apb0-gates-clk {
|
|
compatible = "allwinner,sun8i-a23-apb0-gates-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&apb0>;
|
|
clock-output-names = "apb0_pio", "apb0_timer",
|
|
"apb0_rsb", "apb0_uart",
|
|
"apb0_i2c";
|
|
};
|
|
|
|
apb0_rst: apb0-rst {
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
codec_analog: codec-analog {
|
|
compatible = "allwinner,sun8i-a23-codec-analog";
|
|
};
|
|
};
|
|
|
|
cpucfg@1f01c00 {
|
|
compatible = "allwinner,sun8i-a23-cpuconfig";
|
|
reg = <0x01f01c00 0x300>;
|
|
};
|
|
|
|
r_uart: serial@1f02800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01f02800 0x400>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb0_gates 4>;
|
|
resets = <&apb0_rst 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_i2c: i2c@1f02400 {
|
|
compatible = "allwinner,sun8i-a23-i2c",
|
|
"allwinner,sun6i-a31-i2c";
|
|
reg = <0x01f02400 0x400>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_i2c_pins>;
|
|
clocks = <&apb0_gates 6>;
|
|
resets = <&apb0_rst 6>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
r_pio: pinctrl@1f02c00 {
|
|
compatible = "allwinner,sun8i-a23-r-pinctrl";
|
|
reg = <0x01f02c00 0x400>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
r_i2c_pins: r-i2c-pins {
|
|
pins = "PL0", "PL1";
|
|
function = "s_i2c";
|
|
bias-pull-up;
|
|
};
|
|
|
|
r_rsb_pins: r-rsb-pins {
|
|
pins = "PL0", "PL1";
|
|
function = "s_rsb";
|
|
drive-strength = <20>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
r_uart_pins_a: r-uart-pins {
|
|
pins = "PL2", "PL3";
|
|
function = "s_uart";
|
|
};
|
|
};
|
|
|
|
r_rsb: rsb@1f03400 {
|
|
compatible = "allwinner,sun8i-a23-rsb";
|
|
reg = <0x01f03400 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 3>;
|
|
clock-frequency = <3000000>;
|
|
resets = <&apb0_rst 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_rsb_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|