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https://github.com/u-boot/u-boot.git
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57237c7f41
For some reason the Ethernet PHY reset delay is set to 1 second, this cause an unneccecery long boot delay. Tinker Board use RTL8211E or RTL8211F Ethernet PHY, datasheet list an initial 10ms delay and then a 30-76ms delay before accessing registers. Change to use 80ms delay instead of a full second to speed up Ethernet initializion in U-Boot. Also enable PHY_REALTEK, DM_ETH_PHY and PHY_GIGE to improve Ethernet PHY support in U-Boot. Before: 1,404,971 960,924 eth_common_init 2,438,830 1,033,859 eth_initialize 2,444,449 5,619 main_loop 2,445,153 704 cli_loop After: 1,404,987 960,710 eth_common_init 1,519,110 114,123 eth_initialize 1,524,734 5,624 main_loop 1,525,452 718 cli_loop Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
84 lines
1.2 KiB
Text
84 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Rockchip Electronics Co., Ltd
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*/
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#include "rk3288-u-boot.dtsi"
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&dmc {
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rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
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0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
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0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
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0x8 0x1f4>;
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rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
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0x0 0xc3 0x6 0x2>;
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rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
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};
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&gmac {
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snps,reset-delays-us = <0 10000 80000>;
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};
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&gpio7 {
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/delete-property/ bootph-all;
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};
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&i2c2 {
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m24c08@50 {
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compatible = "at,24c08", "i2c-eeprom";
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reg = <0x50>;
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};
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};
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&pcfg_pull_none {
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bootph-all;
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};
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&pcfg_pull_none_drv_8ma {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pcfg_pull_up {
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bootph-all;
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};
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&pcfg_pull_up_drv_8ma {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc_bus4 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc_cd {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc_clk {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&sdmmc_cmd {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&uart2 {
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bootph-all;
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};
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&uart2_xfer {
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bootph-pre-sram;
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bootph-pre-ram;
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};
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