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Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC. The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts U-Boot proper on the Cortex-A76 core. The SoC BootROM can not boot the CA76 core directly, instead the SPL starts on the CR52 core which immediately brings up the CA76 core, which in turn starts executing the actual SPL. This is achieved by placing a tiny bit of precompiled Aarch32 code at the very beginning of the SPL. The code consists of some 32 instructions, uses APMU to configure CA76 start address to offset 0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The code parts the CR52 core in an endless loop once the CA76 core got started. The 32 instructions are completely arbitrary number, so is the offset 0x80 Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per instruction is 32 instructions. The 32 instructions turned out to be enough to started the CA76 and 0x80 is nicely aligned. Once the SPL completes hardware initialization, the SPL loads U-Boot proper. The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and a DT for R8A779G0 V4H White Hawk board and is generated by binman. The u-boot.itb is loaded from SPI NOR offset 0x80000. In order to install this setup on an existing R8A779G0 V4H White Hawk board, build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin switches according to the R8A779G0 V4H White Hawk board documentation for 40 MHz SPI NOR boot using DMA and restart the board. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
35 lines
434 B
Text
35 lines
434 B
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the White Hawk board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include "r8a779g0-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &rpc;
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};
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};
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&avb1 {
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status = "disabled";
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};
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&avb2 {
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status = "disabled";
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};
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&rpc {
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bootph-all;
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flash@0 {
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bootph-all;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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&qspi0_pins {
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bootph-all;
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};
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