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c9df79ee64
Add 32-bit address overrides for Hyper Bus Memory Controller for Hyperflash to be functional in R5 SPL. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Anurag Dutta <a-dutta@ti.com>
77 lines
1.6 KiB
Text
77 lines
1.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721e-common-proc-board.dts"
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#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
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#include "k3-j721e-ddr.dtsi"
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#include "k3-j721e-common-proc-board-u-boot.dtsi"
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#include "k3-j721e-r5.dtsi"
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&wkup_i2c0 {
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bootph-pre-ram;
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tps659413a: tps659413a@48 {
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reg = <0x48>;
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compatible = "ti,tps659413";
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bootph-pre-ram;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_i2c0_pins_default>;
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clock-frequency = <400000>;
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regulators: regulators {
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bootph-pre-ram;
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buck12_reg: buck12 {
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/*VDD_CPU*/
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regulator-name = "buck12";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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bootph-pre-ram;
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};
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};
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esm: esm {
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compatible = "ti,tps659413-esm";
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bootph-pre-ram;
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};
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};
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};
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&mcu_uart0_pins_default {
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bootph-pre-ram;
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};
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&wkup_vtm0 {
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vdd-supply-2 = <&buck12_reg>;
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bootph-pre-ram;
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};
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&hbmc {
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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ranges = <0x0 0x0 0x0 0x50000000 0x4000000>,
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<0x1 0x0 0x0 0x54000000 0x800000>;
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};
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&ospi0 {
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/* Address change for data region (32-bit) */
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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};
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&ospi1 {
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/* Address change for data region (32-bit) */
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reg = <0x0 0x47050000 0x0 0x100>,
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<0x0 0x58000000 0x0 0x8000000>;
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};
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&fss {
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/* enable ranges missing from the FSS node */
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ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
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<0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
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};
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