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https://github.com/u-boot/u-boot.git
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5d1aac358f
Updated PLL driver sequencing requires us to use udelay in the PLL driver as there is no poll bit to get the status of operations. tick-timer(mcu_timer0/main_timer0) setting up the clocks for itself is something that won't work as the PLL driver will be using udelay and PLLs are configured during clock probe which would end up in a recursive probe. tick-timer being used by K3 devices are configured by ROM and we really don't need to configure any of the clocks. Remove the clock dependency from R5 stage as we don't need to setup clocks for it. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
180 lines
2.2 KiB
Text
180 lines
2.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Common AM62A EVM dts file for SPLs
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am62a-sk-binman.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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};
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memory@80000000 {
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bootph-all;
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};
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};
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&cbass_main {
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bootph-all;
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};
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&dmss {
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bootph-all;
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};
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&secure_proxy_main {
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bootph-all;
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};
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&dmsc {
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bootph-all;
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};
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&k3_pds {
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bootph-all;
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};
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&k3_clks {
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bootph-all;
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};
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&k3_reset {
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bootph-all;
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};
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&wkup_conf {
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bootph-all;
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};
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&chipid {
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bootph-all;
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};
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&main_pmx0 {
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bootph-all;
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};
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&main_uart0 {
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bootph-all;
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};
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&main_uart0_pins_default {
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bootph-all;
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};
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&cbass_mcu {
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bootph-all;
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};
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&cbass_wakeup {
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bootph-all;
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};
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&mcu_pmx0 {
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bootph-all;
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};
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&main_gpio0 {
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bootph-all;
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};
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&main_i2c0 {
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bootph-all;
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};
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&main_i2c0_pins_default {
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bootph-all;
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};
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&main_i2c1 {
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bootph-all;
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};
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&main_i2c1_pins_default {
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bootph-all;
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};
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&exp1 {
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bootph-all;
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};
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&sdhci1 {
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bootph-all;
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};
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&main_mmc1_pins_default {
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bootph-all;
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};
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&k3_reset {
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bootph-all;
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};
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&dmsc {
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bootph-all;
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};
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&vdd_mmc1 {
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bootph-all;
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};
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&main_bcdma {
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reg = <0x00 0x485c0100 0x00 0x100>,
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<0x00 0x4c000000 0x00 0x20000>,
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<0x00 0x4a820000 0x00 0x20000>,
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<0x00 0x4aa40000 0x00 0x20000>,
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<0x00 0x4bc00000 0x00 0x100000>,
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<0x00 0x48600000 0x00 0x8000>,
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<0x00 0x484a4000 0x00 0x2000>,
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<0x00 0x484c2000 0x00 0x2000>;
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reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
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"ringrt" , "cfg", "tchan", "rchan";
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bootph-all;
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};
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&main_pktdma {
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reg = <0x00 0x485c0000 0x00 0x100>,
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<0x00 0x4a800000 0x00 0x20000>,
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<0x00 0x4aa00000 0x00 0x20000>,
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<0x00 0x4b800000 0x00 0x200000>,
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<0x00 0x485e0000 0x00 0x10000>,
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<0x00 0x484a0000 0x00 0x2000>,
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<0x00 0x484c0000 0x00 0x2000>,
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<0x00 0x48430000 0x00 0x1000>;
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
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"cfg", "tchan", "rchan", "rflow";
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bootph-all;
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};
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&main_mdio1_pins_default {
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bootph-all;
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};
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&cpsw3g_mdio {
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bootph-all;
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};
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&cpsw3g_phy0 {
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bootph-all;
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};
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&main_rgmii1_pins_default {
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bootph-all;
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};
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&phy_gmii_sel {
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bootph-all;
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};
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&cpsw3g {
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bootph-all;
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ethernet-ports {
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bootph-all;
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};
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};
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&cpsw_port1 {
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bootph-all;
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};
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