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https://github.com/u-boot/u-boot.git
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6ad83912a4
Enable usb0 in all boot phases for use with DFU. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
194 lines
2.8 KiB
Text
194 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* phyCORE-AM62x dts file for SPLs
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* Copyright (C) 2022 - 2023 Phytec Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>
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*
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* Product homepage:
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* https://www.phytec.com/product/phyboard-am62x
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*/
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#include "k3-am625-phycore-som-binman.dtsi"
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &main_timer0;
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};
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aliases {
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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};
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memory@80000000 {
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bootph-all;
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};
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};
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&cpsw3g {
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bootph-all;
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};
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&cpsw_port1 {
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bootph-all;
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};
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&cpsw_port2 {
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status = "disabled";
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};
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&cpsw3g_phy1 {
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bootph-all;
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};
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&fss {
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bootph-all;
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};
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&main_bcdma {
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bootph-all;
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reg = <0x00 0x485c0100 0x00 0x100>,
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<0x00 0x4c000000 0x00 0x20000>,
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<0x00 0x4a820000 0x00 0x20000>,
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<0x00 0x4aa40000 0x00 0x20000>,
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<0x00 0x4bc00000 0x00 0x100000>,
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<0x00 0x48600000 0x00 0x8000>,
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<0x00 0x484a4000 0x00 0x2000>,
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<0x00 0x484c2000 0x00 0x2000>;
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reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
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"ringrt" , "cfg", "tchan", "rchan";
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};
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&main_gpio0 {
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bootph-all;
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};
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&main_mdio1_pins_default {
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bootph-all;
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};
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&main_i2c0 {
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bootph-all;
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};
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&main_i2c0_pins_default {
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bootph-all;
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};
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&main_mmc0_pins_default {
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bootph-all;
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};
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&main_mmc1_pins_default {
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bootph-all;
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};
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&main_pktdma {
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bootph-all;
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reg = <0x00 0x485c0000 0x00 0x100>,
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<0x00 0x4a800000 0x00 0x20000>,
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<0x00 0x4aa00000 0x00 0x20000>,
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<0x00 0x4b800000 0x00 0x200000>,
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<0x00 0x485e0000 0x00 0x10000>,
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<0x00 0x484a0000 0x00 0x2000>,
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<0x00 0x484c0000 0x00 0x2000>,
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<0x00 0x48430000 0x00 0x1000>;
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
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"cfg", "tchan", "rchan", "rflow";
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};
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&main_rgmii1_pins_default {
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bootph-all;
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};
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&main_timer0 {
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clock-frequency = <25000000>;
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};
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&main_uart0 {
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bootph-all;
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};
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&main_uart0_pins_default {
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bootph-all;
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};
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&main_uart1 {
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bootph-all;
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};
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&main_uart1_pins_default {
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bootph-all;
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};
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&ospi0 {
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bootph-all;
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flash@0 {
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bootph-all;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "ospi.tiboot3";
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reg = <0x00000 0x80000>;
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};
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partition@80000 {
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label = "ospi.tispl";
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reg = <0x080000 0x200000>;
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};
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partition@280000 {
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label = "ospi.u-boot";
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reg = <0x280000 0x400000>;
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};
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partition@680000 {
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label = "ospi.env";
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reg = <0x680000 0x40000>;
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};
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partition@6c0000 {
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label = "ospi.env.backup";
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reg = <0x6c0000 0x40000>;
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};
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};
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};
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};
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&ospi0_pins_default {
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bootph-all;
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};
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&sdhci0 {
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bootph-all;
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};
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&sdhci1 {
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bootph-all;
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};
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&usbss0 {
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bootph-all;
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};
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&usb0 {
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dr_mode = "peripheral";
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bootph-all;
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};
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&vcc_3v3_mmc {
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bootph-all;
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};
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&vcc_5v0_som {
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bootph-all;
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};
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&vddshv5_sdio {
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bootph-all;
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};
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&wkup_uart0 {
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bootph-all;
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};
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