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d509c48b65
Currently, there is an error when the i.MX93 CPU frequency is read: Could not read CPU frequency: -2 CPU: NXP i.MX93(52) Rev1.1 A55 at 0 MHz Fix it by describing the A55 clock nodes in the devicetree, like done on other i.MX SoCs. With this change, the CPU frequency error is gone and it can be correctly retrieved: CPU: NXP i.MX93(52) Rev1.1 A55 at 1700 MHz CPU: Industrial temperature grade (-40C to 105C) at 35C As the upstream imx93.dtsi does not describe the CPU clocks, keep the clock node in imx93-u-boot.dtsi for now. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
111 lines
1.8 KiB
Text
111 lines
1.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
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*/
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/ {
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binman: binman {
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multiple-images;
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};
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};
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&A55_0 {
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clocks = <&clk IMX93_CLK_ARM_PLL>;
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};
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&A55_1 {
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clocks = <&clk IMX93_CLK_ARM_PLL>;
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};
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&binman {
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u-boot-spl-ddr {
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align = <4>;
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align-size = <4>;
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filename = "u-boot-spl-ddr.bin";
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pad-byte = <0xff>;
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u-boot-spl {
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align-end = <4>;
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filename = "u-boot-spl.bin";
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};
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ddr-1d-imem-fw {
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filename = "lpddr4_imem_1d_v202201.bin";
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align-end = <4>;
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type = "blob-ext";
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};
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ddr-1d-dmem-fw {
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filename = "lpddr4_dmem_1d_v202201.bin";
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align-end = <4>;
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type = "blob-ext";
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};
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ddr-2d-imem-fw {
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filename = "lpddr4_imem_2d_v202201.bin";
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align-end = <4>;
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type = "blob-ext";
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};
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ddr-2d-dmem-fw {
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filename = "lpddr4_dmem_2d_v202201.bin";
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align-end = <4>;
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type = "blob-ext";
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};
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};
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spl {
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filename = "spl.bin";
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mkimage {
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args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x2049A000";
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blob {
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filename = "u-boot-spl-ddr.bin";
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};
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};
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};
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u-boot-container {
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filename = "u-boot-container.bin";
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mkimage {
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args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
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blob {
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filename = "u-boot.bin";
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};
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};
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};
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imx-boot {
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filename = "flash.bin";
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pad-byte = <0x00>;
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spl: blob-ext@1 {
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filename = "spl.bin";
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offset = <0x0>;
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align-size = <0x400>;
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align = <0x400>;
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};
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uboot: blob-ext@2 {
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filename = "u-boot-container.bin";
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};
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};
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};
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&tmu {
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compatible = "fsl,imx93-tmu";
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reg = <0x44482000 0x1000>;
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clocks = <&clk IMX93_CLK_TMC_GATE>;
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little-endian;
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fsl,tmu-calibration = <0x0000000e 0x800000da
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0x00000029 0x800000e9
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0x00000056 0x80000102
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0x000000a2 0x8000012a
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0x00000116 0x80000166
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0x00000195 0x800001a7
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0x000001b2 0x800001b6>;
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#thermal-sensor-cells = <1>;
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};
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