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The phyCORE-i.MX 93 is available in various variants (e.g. different ram sizes, eMMC HS400 yes/no). Enable hardware introspection for the imx93-phyboard-segin_defconfig, so that during startup the SOM module variant can be detected, and the hardware can be configured accordingly. The resulting SPL and u-boot binary shall able to boot each phyCORE-i.MX 93 module variant on each carrier board. Finally rename imx93-phyboard-segin_defconfig to imx93-phycore_defconfig, to highlight its SOM scope. Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de>
373 lines
6.8 KiB
Text
373 lines
6.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 PHYTEC Messtechnik GmbH
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* Christoph Stoidner <c.stoidner@phytec.de>
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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*
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* Product homepage:
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https://www.phytec.de/produkte/system-on-modules/phycore-imx-91-93/
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*/
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#include "imx93-u-boot.dtsi"
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/ {
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/*
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* The phyCORE-i.MX93 u-boot uses the imx93-phyboard-segin.dts as
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* reference, but does only make use of its SoM (phyCORE) contained
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* periphery.
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*/
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model = "PHYTEC phyCORE-i.MX93";
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog3>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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aliases {
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ethernet0 = &fec;
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ethernet1 = &eqos;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&{/soc@0} {
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bootph-all;
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bootph-pre-ram;
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};
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&aips1 {
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bootph-pre-ram;
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bootph-all;
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};
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&aips2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&aips3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&iomuxc {
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bootph-pre-ram;
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bootph-some-ram;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2_cd {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2_default {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2_100mhz {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&pinctrl_usdhc2_200mhz {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&lpuart1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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/*
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* Remove once USB support is added to imx93-phyboard-segin.dts upstream.
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*/
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&usbotg1 {
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disable-over-current;
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dr_mode = "otg";
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status = "okay";
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};
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&usbotg2 {
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disable-over-current;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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bootph-pre-ram;
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bootph-some-ram;
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/*
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* Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
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*/
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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};
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&usdhc2 {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,signal-voltage-switch-extra-delay-ms = <8>;
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};
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&lpi2c1 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&lpi2c2 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&lpi2c3 {
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bootph-pre-ram;
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bootph-some-ram;
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};
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&s4muap {
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bootph-pre-ram;
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bootph-some-ram;
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status = "okay";
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};
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&clk {
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bootph-all;
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bootph-pre-ram;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-rates;
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/delete-property/ assigned-clock-parents;
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};
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&osc_32k {
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bootph-all;
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bootph-pre-ram;
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};
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&osc_24m {
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bootph-all;
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bootph-pre-ram;
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};
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&clk_ext1 {
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bootph-all;
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bootph-pre-ram;
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};
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&wdog3 {
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bootph-all;
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bootph-pre-ram;
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};
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/*
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* The two nodes below won't be needed once nxp,pca9451a
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* support is added to the Linux kernel.
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*/
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&iomuxc {
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pinctrl_lpi2c3: lpi2c3grp {
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bootph-pre-ram;
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fsl,pins = <
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MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
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MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
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>;
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};
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pinctrl_pmic: pmicgrp {
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bootph-pre-ram;
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fsl,pins = <
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MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
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>;
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};
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/*
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* Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
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* are added to imx93-phycore-som.dtsi
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*/
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
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>;
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};
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/* need to config the SION for data and cmd pad, refer to ERR052021 */
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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bootph-pre-ram;
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bootph-some-ram;
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
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>;
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};
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};
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&lpi2c3 {
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bootph-pre-ram;
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bootph-some-ram;
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3>;
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status = "okay";
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pmic@25 {
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bootph-pre-ram;
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bootph-some-ram;
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compatible = "nxp,pca9451a";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio4>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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bootph-pre-ram;
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bootph-some-ram;
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buck1: BUCK1 {
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regulator-name = "VDD_SOC";
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regulator-min-microvolt = <610000>;
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regulator-max-microvolt = <950000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "VDDQ_0V6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <600000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4: BUCK4 {
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regulator-name = "VDD_3V3_BUCK";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
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regulator-name = "VDD_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "VDD_1V1";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-name = "PMIC_SNVS_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-name = "VDD_0V8";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-name = "NVCC_SD2";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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eeprom@50 {
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bootph-pre-ram;
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bootph-some-ram;
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compatible = "atmel,24c32";
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reg = <0x50>;
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pagesize = <32>;
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vcc-supply = <&buck4>;
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};
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};
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