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3b7653db7b
Distinguish more clearly between source files meant for producing .dtb from those meant for producing .dtbo. No functional change, as we currently have rules for producing a foo.dtbo from either foo.dts or foo.dtso. Note that in the linux tree, all device tree overlay sources have been renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit 81d362732bac). So this is also a step towards staying closer to linux with respect to both Kbuild and device tree sources. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Marek Vasut <marex@denx.de>
133 lines
2.6 KiB
Text
133 lines
2.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2023 Marek Vasut <marex@denx.de>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx8mp-pinfunc.h"
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&brcmf {
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reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
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};
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&eeprom0 { /* EEPROM with EQoS MAC address */
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compatible = "atmel,24c02";
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pagesize = <16>;
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};
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&eeprom1 { /* EEPROM with FEC MAC address */
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compatible = "atmel,24c02";
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pagesize = <16>;
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};
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&eeprom0wl {
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status = "disabled";
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};
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&eeprom1wl {
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status = "disabled";
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};
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ðphy0f { /* SMSC LAN8740Ai */
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pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
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reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
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reg = <0>;
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};
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ðphy0g { /* Micrel KSZ9131RNXI */
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pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
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reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
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};
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ðphy1f { /* SMSC LAN8740Ai */
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reg = <1>;
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};
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&i2c3 {
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adc@48 {
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compatible = "ti,tla2024";
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interrupts-extended;
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};
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};
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&ioexp {
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status = "disabled";
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};
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®_eth_vio {
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gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pinctrl_enet_vio>;
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pinctrl-names = "default";
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};
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&rv3032 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc>;
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interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
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};
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&uart2 {
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bluetooth {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_bt>;
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shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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&usb_dwc3_0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_vbus>;
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};
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&usdhc1 {
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pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>;
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};
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&iomuxc {
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pinctrl-0 = <&pinctrl_hog_base
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&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
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&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
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&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
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&pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
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/* GPIO_M is connected to CLKOUT2 */
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&pinctrl_dhcom_int>;
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pinctrl_enet_vio: dhcom-enet-vio-grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
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>;
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};
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pinctrl_rtc: dhcom-rtc-grp {
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fsl,pins = <
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/* RTC_#INT Interrupt */
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MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
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>;
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};
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pinctrl_uart2_bt: dhcom-uart2-bt-grp {
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fsl,pins = <
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/* BT_REG_EN */
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MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
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>;
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};
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pinctrl_usb0_vbus: dhcom-usb0-grp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
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>;
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};
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pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp {
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fsl,pins = <
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/* WL_REG_EN */
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MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
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>;
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};
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};
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