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e3e2d662a2
Even though the PL011 UART driver claims to be DM compliant, it does not really a good job with parsing DT nodes. U-Boot seems to adhere to a non-standard binding, either requiring to have a "skip-init" property in the node, or to have an extra "clock" property holding the base *frequency* value for the baud rate generator. DTs in the U-Boot tree seem to have been hacked to match this requirement. The official binding does not mention any of these properties, instead recommends a standard "clocks" property to point to the baud base clock. Some boards use simple "fixed-clock" providers, which U-Boot readily supports, so let's add some simple DM clock code to the PL011 driver to learn the rate of the first clock, as described by the official binding. These clock nodes seem to be not ready very early in the boot process, so provide a fallback value, by re-using the already existing CONFIG_PL011_CLOCK variable. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [trini: Add <clock_legacy.h> for get_bus_freq() for layerscape platforms] Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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| .. | ||
| adc | ||
| ata | ||
| axi | ||
| bios_emulator | ||
| block | ||
| board | ||
| bootcount | ||
| cache | ||
| clk | ||
| core | ||
| cpu | ||
| crypto | ||
| ddr | ||
| demo | ||
| dfu | ||
| dma | ||
| fastboot | ||
| firmware | ||
| fpga | ||
| gpio | ||
| hwspinlock | ||
| i2c | ||
| input | ||
| led | ||
| mailbox | ||
| memory | ||
| misc | ||
| mmc | ||
| mtd | ||
| net | ||
| nvme | ||
| pch | ||
| pci | ||
| pci_endpoint | ||
| phy | ||
| pinctrl | ||
| power | ||
| pwm | ||
| qe | ||
| ram | ||
| remoteproc | ||
| reset | ||
| rng | ||
| rtc | ||
| scsi | ||
| serial | ||
| smem | ||
| soc | ||
| sound | ||
| spi | ||
| spmi | ||
| sysreset | ||
| tee | ||
| thermal | ||
| timer | ||
| tpm | ||
| ufs | ||
| usb | ||
| video | ||
| virtio | ||
| w1 | ||
| w1-eeprom | ||
| watchdog | ||
| Kconfig | ||
| Makefile | ||