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92114d7c0a
Add glue code for TI AM62 to the dwc3 driver; Most code adopted from TI vendor u-boot code. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # on beagle play
125 lines
2.8 KiB
C
125 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TI AM62 specific glue layer for DWC3
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*/
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include "dwc3-generic.h"
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#define USBSS_MODE_CONTROL 0x1c
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#define USBSS_PHY_CONFIG 0x8
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#define USBSS_PHY_VBUS_SEL_MASK GENMASK(2, 1)
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#define USBSS_PHY_VBUS_SEL_SHIFT 1
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#define USBSS_MODE_VALID BIT(0)
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#define PHY_PLL_REFCLK_MASK GENMASK(3, 0)
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static const int dwc3_ti_am62_rate_table[] = { /* in KHZ */
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9600,
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10000,
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12000,
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19200,
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20000,
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24000,
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25000,
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26000,
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38400,
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40000,
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58000,
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50000,
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52000,
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};
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static void dwc3_ti_am62_glue_configure(struct udevice *dev, int index,
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enum usb_dr_mode mode)
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{
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struct clk usb2_refclk;
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int rate_code, i, ret;
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unsigned long rate;
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u32 reg;
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void *usbss;
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bool vbus_divider;
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struct regmap *syscon;
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struct ofnode_phandle_args args;
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usbss = dev_remap_addr_index(dev, 0);
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if (IS_ERR(usbss)) {
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dev_err(dev, "can't map IOMEM resource\n");
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return;
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}
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ret = clk_get_by_name(dev, "ref", &usb2_refclk);
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if (ret) {
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dev_err(dev, "can't get usb2_refclk\n");
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return;
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}
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/* Calculate the rate code */
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rate = clk_get_rate(&usb2_refclk);
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rate /= 1000; /* To KHz */
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for (i = 0; i < ARRAY_SIZE(dwc3_ti_am62_rate_table); i++) {
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if (dwc3_ti_am62_rate_table[i] == rate)
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break;
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}
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if (i == ARRAY_SIZE(dwc3_ti_am62_rate_table)) {
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dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
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return;
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}
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rate_code = i;
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/* Read the syscon property */
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syscon = syscon_regmap_lookup_by_phandle(dev, "ti,syscon-phy-pll-refclk");
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if (IS_ERR(syscon)) {
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dev_err(dev, "unable to get ti,syscon-phy-pll-refclk regmap\n");
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return;
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}
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ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "ti,syscon-phy-pll-refclk", NULL, 1,
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0, &args);
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if (ret)
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return;
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/* Program PHY PLL refclk by reading syscon property */
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ret = regmap_update_bits(syscon, args.args[0], PHY_PLL_REFCLK_MASK, rate_code);
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if (ret) {
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dev_err(dev, "failed to set phy pll reference clock rate\n");
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return;
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}
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/* VBUS divider select */
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reg = readl(usbss + USBSS_PHY_CONFIG);
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vbus_divider = dev_read_bool(dev, "ti,vbus-divider");
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if (vbus_divider)
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reg |= 1 << USBSS_PHY_VBUS_SEL_SHIFT;
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writel(reg, usbss + USBSS_PHY_CONFIG);
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/* Set mode valid */
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reg = readl(usbss + USBSS_MODE_CONTROL);
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reg |= USBSS_MODE_VALID;
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writel(reg, usbss + USBSS_MODE_CONTROL);
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}
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struct dwc3_glue_ops ti_am62_ops = {
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.glue_configure = dwc3_ti_am62_glue_configure,
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};
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static const struct udevice_id dwc3_am62_match[] = {
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{ .compatible = "ti,am62-usb", .data = (ulong)&ti_am62_ops },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(dwc3_am62_wrapper) = {
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.name = "dwc3-am62",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = dwc3_am62_match,
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.bind = dwc3_glue_bind,
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.probe = dwc3_glue_probe,
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.remove = dwc3_glue_remove,
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.plat_auto = sizeof(struct dwc3_glue_data),
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};
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