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https://github.com/u-boot/u-boot.git
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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
609 lines
14 KiB
C
609 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <clk.h>
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#include <dm/device_compat.h>
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#include <log.h>
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#include <malloc.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <soc.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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struct cpsw_mdio_regs {
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u32 version;
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u32 control;
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#define CONTROL_IDLE BIT(31)
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#define CONTROL_ENABLE BIT(30)
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#define CONTROL_FAULT BIT(19)
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#define CONTROL_FAULT_ENABLE BIT(18)
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#define CONTROL_DIV_MASK GENMASK(15, 0)
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#define CONTROL_MAX_DIV CONTROL_DIV_MASK
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#define MDIO_MAN_MDCLK_O BIT(2)
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#define MDIO_MAN_OE BIT(1)
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#define MDIO_MAN_PIN BIT(0)
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#define MDIO_MANUALMODE BIT(31)
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u32 alive;
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u32 link;
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u32 linkintraw;
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u32 linkintmasked;
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u32 __reserved_0[2];
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u32 userintraw;
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u32 userintmasked;
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u32 userintmaskset;
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u32 userintmaskclr;
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u32 manualif;
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u32 poll;
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u32 __reserved_1[18];
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struct {
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u32 access;
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u32 physel;
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#define USERACCESS_GO BIT(31)
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#define USERACCESS_WRITE BIT(30)
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#define USERACCESS_ACK BIT(29)
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#define USERACCESS_READ (0)
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#define USERACCESS_PHY_REG_SHIFT (21)
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#define USERACCESS_PHY_ADDR_SHIFT (16)
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#define USERACCESS_DATA GENMASK(15, 0)
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} user[2];
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};
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#define CPSW_MDIO_DIV_DEF 0xff
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#define PHY_REG_MASK 0x1f
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#define PHY_ID_MASK 0x1f
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#define MDIO_BITRANGE 0x8000
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#define C22_READ_PATTERN 0x6
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#define C22_WRITE_PATTERN 0x5
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#define C22_BITRANGE 0x8
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#define PHY_BITRANGE 0x10
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#define PHY_DATA_BITRANGE 0x8000
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/*
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* This timeout definition is a worst-case ultra defensive measure against
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* unexpected controller lock ups. Ideally, we should never ever hit this
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* scenario in practice.
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*/
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#define CPSW_MDIO_TIMEOUT 100 /* msecs */
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#define CPSW_MDIO_DEF_BUS_FREQ 2200000 /* 2.2 MHz */
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enum cpsw_mdio_manual {
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MDIO_PIN = 0,
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MDIO_OE,
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MDIO_MDCLK,
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};
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struct cpsw_mdio {
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struct cpsw_mdio_regs *regs;
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struct mii_dev *bus;
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int div;
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bool manual_mode;
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struct clk clk;
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unsigned long bus_freq;
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};
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static int cpsw_mdio_enable(struct cpsw_mdio *data)
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{
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int ret;
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/* set enable and clock divider */
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writel(data->div | CONTROL_ENABLE, &data->regs->control);
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ret = wait_for_bit_le32(&data->regs->control,
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CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true);
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if (ret)
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return ret;
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/*
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* wait for scan logic to settle:
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* the scan time consists of (a) a large fixed component, and (b) a
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* small component that varies with the mii bus frequency. These
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* were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
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* silicon. Since the effect of (b) was found to be largely
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* negligible, we keep things simple here.
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*/
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mdelay(1);
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return 0;
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}
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static void cpsw_mdio_disable(struct cpsw_mdio *mdio)
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{
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u32 reg;
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/* Disable MDIO state machine */
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reg = readl(&mdio->regs->control);
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reg &= ~CONTROL_ENABLE;
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writel(reg, &mdio->regs->control);
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}
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static void cpsw_mdio_enable_manual_mode(struct cpsw_mdio *mdio)
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{
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u32 reg;
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/* set manual mode */
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reg = readl(&mdio->regs->poll);
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reg |= MDIO_MANUALMODE;
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writel(reg, &mdio->regs->poll);
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}
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static void cpsw_mdio_sw_set_bit(struct cpsw_mdio *mdio,
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enum cpsw_mdio_manual bit)
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{
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u32 reg;
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reg = readl(&mdio->regs->manualif);
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switch (bit) {
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case MDIO_OE:
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reg |= MDIO_MAN_OE;
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writel(reg, &mdio->regs->manualif);
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break;
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case MDIO_PIN:
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reg |= MDIO_MAN_PIN;
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writel(reg, &mdio->regs->manualif);
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break;
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case MDIO_MDCLK:
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reg |= MDIO_MAN_MDCLK_O;
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writel(reg, &mdio->regs->manualif);
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break;
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default:
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break;
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};
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}
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static void cpsw_mdio_sw_clr_bit(struct cpsw_mdio *mdio,
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enum cpsw_mdio_manual bit)
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{
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u32 reg;
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reg = readl(&mdio->regs->manualif);
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switch (bit) {
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case MDIO_OE:
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reg &= ~MDIO_MAN_OE;
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writel(reg, &mdio->regs->manualif);
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break;
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case MDIO_PIN:
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reg &= ~MDIO_MAN_PIN;
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writel(reg, &mdio->regs->manualif);
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break;
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case MDIO_MDCLK:
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reg = readl(&mdio->regs->manualif);
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reg &= ~MDIO_MAN_MDCLK_O;
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writel(reg, &mdio->regs->manualif);
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break;
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default:
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break;
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};
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}
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static int cpsw_mdio_test_man_bit(struct cpsw_mdio *mdio,
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enum cpsw_mdio_manual bit)
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{
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u32 reg;
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reg = readl(&mdio->regs->manualif);
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return test_bit(bit, ®);
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}
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static void cpsw_mdio_toggle_man_bit(struct cpsw_mdio *mdio,
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enum cpsw_mdio_manual bit)
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{
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cpsw_mdio_sw_clr_bit(mdio, bit);
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cpsw_mdio_sw_set_bit(mdio, bit);
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}
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static void cpsw_mdio_man_send_pattern(struct cpsw_mdio *mdio,
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u32 bitrange, u32 val)
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{
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u32 i;
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for (i = bitrange; i; i = i >> 1) {
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if (i & val)
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cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
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else
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cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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}
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}
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static void cpsw_mdio_sw_preamble(struct cpsw_mdio *mdio)
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{
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u32 i;
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cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
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for (i = 0; i < 32; i++) {
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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}
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}
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#if defined(CONFIG_DM_MDIO)
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#define MII_TO_CPSW_MDIO(bus) (dev_get_priv((struct udevice *)(bus)->priv))
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#else
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#define MII_TO_CPSW_MDIO(bus) ((bus)->priv)
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#endif
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static int cpsw_mdio_sw_read(struct mii_dev *bus, int phy_id,
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int dev_addr, int phy_reg)
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{
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struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
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u32 reg, i;
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u8 ack;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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cpsw_mdio_disable(mdio);
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cpsw_mdio_enable_manual_mode(mdio);
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cpsw_mdio_sw_preamble(mdio);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
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/* Issue clause 22 MII read function {0,1,1,0} */
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cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_READ_PATTERN);
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/* Send the device number MSB first */
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cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
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/* Send the register number MSB first */
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cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
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/* Send turn around cycles */
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cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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ack = cpsw_mdio_test_man_bit(mdio, MDIO_PIN);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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reg = 0;
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if (ack == 0) {
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for (i = MDIO_BITRANGE; i; i = i >> 1) {
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if (cpsw_mdio_test_man_bit(mdio, MDIO_PIN))
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reg |= i;
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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}
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} else {
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for (i = MDIO_BITRANGE; i; i = i >> 1)
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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reg = 0xFFFF;
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}
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_set_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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return reg;
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}
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static int cpsw_mdio_sw_write(struct mii_dev *bus, int phy_id,
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int dev_addr, int phy_reg, u16 phy_data)
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{
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struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
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if ((phy_reg & ~PHY_REG_MASK) || (phy_id & ~PHY_ID_MASK))
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return -EINVAL;
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cpsw_mdio_disable(mdio);
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cpsw_mdio_enable_manual_mode(mdio);
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cpsw_mdio_sw_preamble(mdio);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_set_bit(mdio, MDIO_OE);
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/* Issue clause 22 MII write function {0,1,0,1} */
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cpsw_mdio_man_send_pattern(mdio, C22_BITRANGE, C22_WRITE_PATTERN);
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/* Send the device number MSB first */
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cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_id);
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/* Send the register number MSB first */
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cpsw_mdio_man_send_pattern(mdio, PHY_BITRANGE, phy_reg);
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/* set turn-around cycles */
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cpsw_mdio_sw_set_bit(mdio, MDIO_PIN);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_PIN);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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/* Send Register data MSB first */
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cpsw_mdio_man_send_pattern(mdio, PHY_DATA_BITRANGE, phy_data);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_OE);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_sw_clr_bit(mdio, MDIO_MDCLK);
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cpsw_mdio_toggle_man_bit(mdio, MDIO_MDCLK);
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return 0;
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}
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/* wait until hardware is ready for another user access */
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static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
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{
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return wait_for_bit_le32(&mdio->regs->user[0].access,
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USERACCESS_GO, false,
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CPSW_MDIO_TIMEOUT, false);
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}
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static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
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int dev_addr, int phy_reg)
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{
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struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
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int data, ret;
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u32 reg;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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ret = cpsw_mdio_wait_for_user_access(mdio);
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if (ret)
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return ret;
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reg = (USERACCESS_GO | USERACCESS_READ |
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(phy_reg << USERACCESS_PHY_REG_SHIFT) |
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(phy_id << USERACCESS_PHY_ADDR_SHIFT));
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writel(reg, &mdio->regs->user[0].access);
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ret = cpsw_mdio_wait_for_user_access(mdio);
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if (ret)
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return ret;
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reg = readl(&mdio->regs->user[0].access);
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data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
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return data;
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}
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static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
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int phy_reg, u16 data)
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{
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struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
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u32 reg;
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int ret;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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ret = cpsw_mdio_wait_for_user_access(mdio);
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if (ret)
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return ret;
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reg = (USERACCESS_GO | USERACCESS_WRITE |
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(phy_reg << USERACCESS_PHY_REG_SHIFT) |
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(phy_id << USERACCESS_PHY_ADDR_SHIFT) |
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(data & USERACCESS_DATA));
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writel(reg, &mdio->regs->user[0].access);
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return cpsw_mdio_wait_for_user_access(mdio);
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}
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#if !defined(CONFIG_MDIO_TI_CPSW)
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u32 cpsw_mdio_get_alive(struct mii_dev *bus)
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{
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struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
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u32 val;
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val = readl(&mdio->regs->alive);
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return val & GENMASK(7, 0);
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}
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struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
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u32 bus_freq, int fck_freq, bool manual_mode)
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{
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struct cpsw_mdio *cpsw_mdio;
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int ret;
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cpsw_mdio = calloc(1, sizeof(*cpsw_mdio));
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if (!cpsw_mdio) {
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debug("failed to alloc cpsw_mdio\n");
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return NULL;
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}
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cpsw_mdio->bus = mdio_alloc();
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if (!cpsw_mdio->bus) {
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debug("failed to alloc mii bus\n");
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free(cpsw_mdio);
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return NULL;
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}
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cpsw_mdio->regs = (struct cpsw_mdio_regs *)(uintptr_t)mdio_base;
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if (!bus_freq || !fck_freq)
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cpsw_mdio->div = CPSW_MDIO_DIV_DEF;
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else
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cpsw_mdio->div = (fck_freq / bus_freq) - 1;
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cpsw_mdio->div &= CONTROL_DIV_MASK;
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ret = cpsw_mdio_enable(cpsw_mdio);
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if (ret) {
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debug("mdio_enable failed: %d\n", ret);
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goto free_bus;
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}
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if (manual_mode) {
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cpsw_mdio->bus->read = cpsw_mdio_sw_read;
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cpsw_mdio->bus->write = cpsw_mdio_sw_write;
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} else {
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cpsw_mdio->bus->read = cpsw_mdio_read;
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cpsw_mdio->bus->write = cpsw_mdio_write;
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}
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cpsw_mdio->bus->priv = cpsw_mdio;
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snprintf(cpsw_mdio->bus->name, sizeof(cpsw_mdio->bus->name), name);
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ret = mdio_register(cpsw_mdio->bus);
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if (ret < 0) {
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debug("failed to register mii bus\n");
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goto free_bus;
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}
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return cpsw_mdio->bus;
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free_bus:
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mdio_free(cpsw_mdio->bus);
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free(cpsw_mdio);
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return NULL;
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}
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void cpsw_mdio_free(struct mii_dev *bus)
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{
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struct cpsw_mdio *mdio = bus->priv;
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u32 reg;
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/* disable mdio */
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reg = readl(&mdio->regs->control);
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reg &= ~CONTROL_ENABLE;
|
|
writel(reg, &mdio->regs->control);
|
|
|
|
mdio_unregister(bus);
|
|
mdio_free(bus);
|
|
free(mdio);
|
|
}
|
|
|
|
#else
|
|
|
|
static int cpsw_mdio_init_clk(struct cpsw_mdio *data)
|
|
{
|
|
u32 mdio_in, div;
|
|
|
|
mdio_in = clk_get_rate(&data->clk);
|
|
div = (mdio_in / data->bus_freq) - 1;
|
|
if (div > CONTROL_MAX_DIV)
|
|
div = CONTROL_MAX_DIV;
|
|
|
|
data->div = div;
|
|
return cpsw_mdio_enable(data);
|
|
}
|
|
|
|
static int cpsw_mdio_bus_read(struct udevice *dev, int addr,
|
|
int devad, int reg)
|
|
{
|
|
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
|
NULL;
|
|
struct cpsw_mdio *priv = dev_get_priv(dev);
|
|
|
|
if (pdata && pdata->mii_bus) {
|
|
if (priv->manual_mode)
|
|
return cpsw_mdio_sw_read(pdata->mii_bus, addr, devad, reg);
|
|
else
|
|
return cpsw_mdio_read(pdata->mii_bus, addr, devad, reg);
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int cpsw_mdio_bus_write(struct udevice *dev, int addr,
|
|
int devad, int reg, u16 val)
|
|
{
|
|
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
|
NULL;
|
|
struct cpsw_mdio *priv = dev_get_priv(dev);
|
|
|
|
if (pdata && pdata->mii_bus) {
|
|
if (priv->manual_mode)
|
|
return cpsw_mdio_sw_write(pdata->mii_bus, addr, devad, reg, val);
|
|
else
|
|
return cpsw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static const struct mdio_ops cpsw_mdio_ops = {
|
|
.read = cpsw_mdio_bus_read,
|
|
.write = cpsw_mdio_bus_write,
|
|
};
|
|
|
|
static const struct soc_attr k3_mdio_soc_data[] = {
|
|
{ .family = "AM62X", .revision = "SR1.0" },
|
|
{ .family = "AM64X", .revision = "SR1.0" },
|
|
{ .family = "AM64X", .revision = "SR2.0" },
|
|
{ .family = "AM65X", .revision = "SR1.0" },
|
|
{ .family = "AM65X", .revision = "SR2.0" },
|
|
{ .family = "J7200", .revision = "SR1.0" },
|
|
{ .family = "J7200", .revision = "SR2.0" },
|
|
{ .family = "J721E", .revision = "SR1.0" },
|
|
{ .family = "J721E", .revision = "SR1.1" },
|
|
{ .family = "J721S2", .revision = "SR1.0" },
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static const struct udevice_id cpsw_mdio_ids[] = {
|
|
{ .compatible = "ti,davinci_mdio", },
|
|
{ .compatible = "ti,cpsw-mdio", },
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
static int cpsw_mdio_probe(struct udevice *dev)
|
|
{
|
|
struct cpsw_mdio *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
if (!priv) {
|
|
dev_err(dev, "dev_get_priv(dev %p) = NULL\n", dev);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
priv->regs = dev_remap_addr(dev);
|
|
|
|
if (soc_device_match(k3_mdio_soc_data))
|
|
priv->manual_mode = true;
|
|
|
|
ret = clk_get_by_name(dev, "fck", &priv->clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get clock %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
priv->bus_freq = dev_read_u32_default(dev, "bus_freq",
|
|
CPSW_MDIO_DEF_BUS_FREQ);
|
|
ret = cpsw_mdio_init_clk(priv);
|
|
if (ret) {
|
|
dev_err(dev, "init clock failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpsw_mdio_remove(struct udevice *dev)
|
|
{
|
|
struct cpsw_mdio *priv = dev_get_priv(dev);
|
|
|
|
cpsw_mdio_disable(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(cpsw_mdio) = {
|
|
.name = "cpsw_mdio",
|
|
.id = UCLASS_MDIO,
|
|
.of_match = cpsw_mdio_ids,
|
|
.probe = cpsw_mdio_probe,
|
|
.remove = cpsw_mdio_remove,
|
|
.ops = &cpsw_mdio_ops,
|
|
.priv_auto = sizeof(struct cpsw_mdio),
|
|
};
|
|
#endif /* CONFIG_MDIO_TI_CPSW */
|