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40f5046c22
Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2 cpu core each. A lot of IPs are shared with previous families. There are couple of new IP blocks where the most interesting from user point of view is UFS. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com
34 lines
706 B
C
34 lines
706 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 - 2022, Xilinx, Inc.
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* Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <init.h>
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#include <time.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CLOCKS
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/**
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* set_cpu_clk_info - Initialize clock framework
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*
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* Return: 0 always.
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*
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* This function is called from common code after relocation and sets up the
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* clock framework. The framework must not be used before this function had been
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* called.
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*/
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int set_cpu_clk_info(void)
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{
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gd->cpu_clk = get_tbclk();
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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#endif
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