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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
196 lines
5.4 KiB
C
196 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include <spl.h>
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#include "../common/imx8m_som_detection.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define EEPROM_ADDR 0x51
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#define EEPROM_ADDR_FALLBACK 0x59
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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int ret;
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ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
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EEPROM_ADDR_FALLBACK);
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if (ret)
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goto out;
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ret = phytec_imx8m_detect(NULL);
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if (!ret)
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phytec_print_som_info(NULL);
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u8 rev = phytec_get_rev(NULL);
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u8 somtype = phytec_get_som_type(NULL);
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if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) {
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dram_timing.ddrc_cfg[3].val = 0x1323;
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dram_timing.ddrc_cfg[4].val = 0x1e84800;
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dram_timing.ddrc_cfg[5].val = 0x7a0118;
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dram_timing.ddrc_cfg[8].val = 0xc00307a3;
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dram_timing.ddrc_cfg[9].val = 0xc50000;
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dram_timing.ddrc_cfg[10].val = 0xf4003f;
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dram_timing.ddrc_cfg[11].val = 0xf30000;
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dram_timing.ddrc_cfg[14].val = 0x2028222a;
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dram_timing.ddrc_cfg[15].val = 0x8083f;
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dram_timing.ddrc_cfg[16].val = 0xe0e000;
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dram_timing.ddrc_cfg[17].val = 0x12040a12;
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dram_timing.ddrc_cfg[18].val = 0x2050f0f;
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dram_timing.ddrc_cfg[19].val = 0x1010009;
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dram_timing.ddrc_cfg[20].val = 0x502;
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dram_timing.ddrc_cfg[21].val = 0x20800;
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dram_timing.ddrc_cfg[22].val = 0xe100002;
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dram_timing.ddrc_cfg[23].val = 0x120;
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dram_timing.ddrc_cfg[24].val = 0xc80064;
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dram_timing.ddrc_cfg[25].val = 0x3e8001e;
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dram_timing.ddrc_cfg[26].val = 0x3207a12;
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dram_timing.ddrc_cfg[28].val = 0x4a3820e;
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dram_timing.ddrc_cfg[30].val = 0x230e;
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dram_timing.ddrc_cfg[37].val = 0x799;
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dram_timing.ddrc_cfg[38].val = 0x9141d1c;
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dram_timing.ddrc_cfg[74].val = 0x302;
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dram_timing.ddrc_cfg[83].val = 0x599;
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dram_timing.ddrc_cfg[99].val = 0x302;
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dram_timing.ddrc_cfg[108].val = 0x599;
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dram_timing.ddrphy_cfg[66].val = 0x18;
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dram_timing.ddrphy_cfg[75].val = 0x1e3;
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dram_timing.ddrphy_cfg[77].val = 0x1e3;
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dram_timing.ddrphy_cfg[79].val = 0x1e3;
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dram_timing.ddrphy_cfg[145].val = 0x3e8;
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dram_timing.fsp_msg[0].drate = 4000;
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dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
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dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
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dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
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dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
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dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
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dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
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dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
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dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
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dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
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dram_timing.fsp_msg[3].drate = 4000;
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dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
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dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
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dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
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dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
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dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
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dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
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dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
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dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
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dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
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dram_timing.ddrphy_pie[480].val = 0x465;
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dram_timing.ddrphy_pie[481].val = 0xfa;
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dram_timing.ddrphy_pie[482].val = 0x9c4;
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dram_timing.fsp_table[0] = 4000;
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}
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out:
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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ret = power_pca9450_init(0, 0x25);
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if (ret)
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printf("power init failed");
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p = pmic_get("PCA9450");
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pmic_probe(p);
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
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/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
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pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
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/* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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/* Set WDOG_B_CFG to cold reset */
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pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
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return 0;
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}
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void spl_board_init(void)
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{
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/* Set GIC clock to 500Mhz for OD VDD_SOC. */
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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}
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int board_fit_config_name_match(const char *name)
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{
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(0);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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}
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