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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
89 lines
2.6 KiB
C
89 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
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CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
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CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
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CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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#ifdef CONFIG_SPL_NAND_BOOT
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SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_4K, 1),
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#endif
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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#ifndef CONFIG_SPL_BUILD
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SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000,
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CFG_SYS_FLASH_BASE_PHYS + 0x1000000,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 3, BOOKE_PAGESZ_16M, 1),
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#ifdef CONFIG_PCI
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCI I/O */
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SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256K, 1),
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#endif
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#endif
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/* *I*G - Board CPLD */
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SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_1M, 1),
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#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
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SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
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0, 8, BOOKE_PAGESZ_1G, 1),
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#endif
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#ifdef CFG_SYS_INIT_L2_ADDR
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/* *I*G - L2SRAM */
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SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 11, BOOKE_PAGESZ_256K, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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