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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <command.h>
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#include <init.h>
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#include <malloc.h>
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#include <asm/global_data.h>
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#include <asm/immap.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard (void) {
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ulong val;
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uchar val8;
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puts ("Board: ");
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puts("Freescale M5249EVB");
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val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
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printf(" (Switch=%1X)\n", val8);
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/*
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* Set LED on
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*/
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val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED;
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mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
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return 0;
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};
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int dram_init(void)
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{
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unsigned long junk = 0xa5a59696;
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/*
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* Note:
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* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
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*/
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#ifdef CFG_SYS_FAST_CLK
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/*
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* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
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*/
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mbar_writeShort(MCFSIM_DCR, 0x8239);
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#elif CFG_SYS_PLL_BYPASS
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/*
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* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
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*/
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mbar_writeShort(MCFSIM_DCR, 0x8202);
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#else
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/*
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* Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
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* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
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*/
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mbar_writeShort(MCFSIM_DCR, 0x8222);
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#endif
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/*
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* SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
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* PM=1 (continuous page mode)
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*/
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/* RE=0 (keep auto-refresh disabled while setting up registers) */
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mbar_writeLong(MCFSIM_DACR0, 0x00003324);
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/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
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mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
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/** Precharge sequence **/
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mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
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*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
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udelay(0x10); /* Allow several Precharge cycles */
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/** Refresh Sequence **/
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mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
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udelay(0x7d0); /* Allow gobs of refresh cycles */
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/** Mode Register initialization **/
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mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
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*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
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gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
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return 0;
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};
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf ("DRAM test not implemented!\n");
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return (0);
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}
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