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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
146 lines
3.1 KiB
C
146 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2018-2019, 2021 NXP
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*
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*/
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#include <common.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/ddr.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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arch_misc_init();
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/*
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* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
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* not allow to change it. Should set the clock after PMIC
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* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
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* set by ROM for ND VDD_SOC
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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puts("Normal Boot\n");
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pmic@25", &dev);
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if (ret == -ENODEV) {
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puts("No pmic@25\n");
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return 0;
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}
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if (ret < 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/*
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* Increase VDD_SOC to typical value 0.95V before first
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* DRAM access, set DVS1 to 0.85V for suspend.
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
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*/
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if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV))
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
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else
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/*
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* Kernel uses OD/OD freq for SOC.
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* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD
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* voltage 0.95V.
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*/
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pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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/* Do not use BSS area in this phase */
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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ret = spl_early_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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}
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