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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
139 lines
3.1 KiB
C
139 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Cisco Systems, Inc.
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* (C) Copyright 2019 Synamedia
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*
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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*/
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#include <cpu_func.h>
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#include <init.h>
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#include <log.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include <linux/types.h>
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#include <common.h>
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#include <env.h>
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#include <asm/io.h>
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#include <asm/bootm.h>
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#include <mach/timer.h>
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#include <mmc.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BCMSTB_DATA_SECTION __section(".data")
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struct bcmstb_boot_parameters bcmstb_boot_parameters BCMSTB_DATA_SECTION;
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phys_addr_t prior_stage_fdt_address BCMSTB_DATA_SECTION;
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union reg_value_union {
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const char *data;
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const phys_addr_t *address;
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};
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int board_init(void)
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{
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return 0;
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}
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void reset_cpu(void)
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{
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}
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int print_cpuinfo(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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/*
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* On this SoC, U-Boot is running as an ELF file. Change the
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* relocation address to CONFIG_TEXT_BASE, so that in
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* setup_reloc, gd->reloc_off works out to 0, effectively
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* disabling relocation. Otherwise U-Boot hangs in the setup
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* instructions just before relocate_code in
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* arch/arm/lib/crt0.S.
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*/
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gd->relocaddr = CONFIG_TEXT_BASE;
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return 0;
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}
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void enable_caches(void)
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{
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/*
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* This port assumes that the prior stage bootloader has
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* enabled I-cache and D-cache already. Implementing this
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* function silences the warning in the default function.
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*/
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}
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int timer_init(void)
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{
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gd->arch.timer_rate_hz = readl(BCMSTB_TIMER_FREQUENCY);
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return 0;
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}
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ulong get_tbclk(void)
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{
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return gd->arch.timer_rate_hz;
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}
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uint64_t get_ticks(void)
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{
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gd->timebase_h = readl(BCMSTB_TIMER_HIGH);
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gd->timebase_l = readl(BCMSTB_TIMER_LOW);
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return ((uint64_t)gd->timebase_h << 32) | gd->timebase_l;
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}
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int board_late_init(void)
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{
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debug("Arguments from prior stage bootloader:\n");
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debug("General Purpose Register 0: 0x%x\n", bcmstb_boot_parameters.r0);
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debug("General Purpose Register 1: 0x%x\n", bcmstb_boot_parameters.r1);
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debug("General Purpose Register 2: 0x%x\n", bcmstb_boot_parameters.r2);
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debug("General Purpose Register 3: 0x%x\n", bcmstb_boot_parameters.r3);
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debug("Stack Pointer Register: 0x%x\n", bcmstb_boot_parameters.sp);
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debug("Link Register: 0x%x\n", bcmstb_boot_parameters.lr);
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debug("Assuming timer frequency register at: 0x%p\n",
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(void *)BCMSTB_TIMER_FREQUENCY);
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debug("Read timer frequency (in Hz): %ld\n", gd->arch.timer_rate_hz);
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debug("Prior stage provided DTB at: 0x%p\n",
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(void *)prior_stage_fdt_address);
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/*
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* Set fdtcontroladdr in the environment so that scripts can
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* refer to it, for example, to reuse it for fdtaddr.
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*/
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env_set_hex("fdtcontroladdr", prior_stage_fdt_address);
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/*
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* Do not set machid to the machine identifier value provided
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* by the prior stage bootloader (bcmstb_boot_parameters.r1)
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* because we're using a device tree to boot Linux.
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*/
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return 0;
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}
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void *board_fdt_blob_setup(int *err)
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{
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*err = 0;
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/* Stored the DTB address there during our init */
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return (void *)prior_stage_fdt_address;
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}
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