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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
257 lines
6.3 KiB
C
257 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Copyright 2022 Linaro
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <errno.h>
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#include <fsl_esdhc_imx.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <mmc.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <dm/uclass.h>
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#include <linux/delay.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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#ifdef CONFIG_SPL_BOOTROM_SUPPORT
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return BOOT_DEVICE_BOOTROM;
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#else
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switch (boot_dev_spl) {
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case SD1_BOOT:
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case MMC1_BOOT:
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC2;
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case QSPI_BOOT:
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return BOOT_DEVICE_NOR;
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case NAND_BOOT:
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return BOOT_DEVICE_NAND;
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case USB_BOOT:
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return BOOT_DEVICE_BOARD;
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default:
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return BOOT_DEVICE_NONE;
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}
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#endif
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
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#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
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#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
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PAD_CTL_PE | \
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PAD_CTL_FSEL2)
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#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
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#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS | \
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PAD_CTL_DSE4)
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static const iomux_v3_cfg_t usdhc3_pads[] = {
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MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static const iomux_v3_cfg_t usdhc2_pads[] = {
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MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
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MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
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};
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#ifndef USDHC3_BASE_ADDR
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#define USDHC3_BASE_ADDR 0x30B60000
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#endif
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC2_BASE_ADDR, 0, 4},
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{USDHC3_BASE_ADDR, 0, 8},
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};
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int board_mmc_init(struct bd_info *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc1 USDHC2
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*/
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for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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init_clk_usdhc(1);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
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ARRAY_SIZE(usdhc2_pads));
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gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
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gpio_direction_output(USDHC2_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC2_PWR_GPIO, 1);
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gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
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gpio_direction_input(USDHC2_CD_GPIO);
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break;
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case 1:
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init_clk_usdhc(2);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
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ARRAY_SIZE(usdhc3_pads));
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break;
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default:
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printf("Warning: you configured more USDHC controllers");
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printf("(%d) than supported by the board\n", i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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default:
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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return ret;
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}
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return 1;
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}
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int power_init_board(void)
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{
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struct udevice *pdev;
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int ret;
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ret = pmic_get("pca9450@25", &pdev);
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if (ret == -ENODEV) {
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printf("No pmic\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(pdev, PCA9450_BUCK123_DVS, 0x29);
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/*
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* increase VDD_SOC to typical value 0.95V before first
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* DRAM access, set DVS1 to 0.85v for suspend.
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
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*/
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pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS0, 0x1C);
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pmic_reg_write(pdev, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(pdev, PCA9450_BUCK1CTRL, 0x59);
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/* Kernel uses OD/OD freq for SOC */
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/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
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pmic_reg_write(pdev, PCA9450_BUCK2OUT_DVS0, 0x1C);
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/* Forced enable the I2C level translator*/
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pmic_reg_write(pdev, PCA9450_CONFIG2, 0x03);
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return 0;
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}
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void spl_board_init(void)
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{
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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board_early_init_f();
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timer_init();
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ret = spl_early_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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}
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