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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
163 lines
3.7 KiB
C
163 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Net Insight <www.netinsight.net>
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* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
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*
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* Based on sheevaplug.c:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/mach-types.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include "openrd.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(OPENRD_OE_VAL_LOW,
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OPENRD_OE_VAL_HIGH,
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OPENRD_OE_LOW, OPENRD_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD, /* Alt UART1_TXD */
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MPP14_SD_D0, /* Alt UART1_RXD */
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GE1_0,
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MPP21_GE1_1,
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MPP22_GE1_2,
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MPP23_GE1_3,
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MPP24_GE1_4,
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MPP25_GE1_5,
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MPP26_GE1_6,
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MPP27_GE1_7,
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MPP28_GPIO,
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MPP29_TSMP9,
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MPP30_GE1_10,
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MPP31_GE1_11,
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MPP32_GE1_12,
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MPP33_GE1_13,
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MPP34_GPIO, /* UART1 / SD sel */
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MPP35_TDM_CH0_TX_QL,
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MPP36_TDM_SPI_CS1,
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MPP37_TDM_CH2_TX_QL,
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MPP38_TDM_CH2_RX_QL,
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MPP39_AUDIO_I2SBCLK,
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MPP40_AUDIO_I2SDO,
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MPP41_AUDIO_I2SLRC,
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MPP42_AUDIO_I2SMCLK,
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MPP43_AUDIO_I2SDI,
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MPP44_AUDIO_EXTCLK,
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MPP45_TDM_PCLK,
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MPP46_TDM_FS,
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MPP47_TDM_DRX,
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MPP48_TDM_DTX,
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MPP49_TDM_CH0_RX_QL,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/*
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* arch number of board
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*/
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#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
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gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
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#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
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gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
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#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
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gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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/* Configure and enable MV88E1116/88E1121 PHY */
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void mv_phy_init(char *name)
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{
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u16 reg;
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u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
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printf("Err..%s could not read PHY dev address\n", __func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("Initialized on %s\n", name);
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}
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void reset_phy(void)
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{
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mv_phy_init("egiga0");
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#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
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/* Kirkwood ethernet driver is written with the assumption that in case
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* of multiple PHYs, their addresses are consecutive. But unfortunately
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* in case of OpenRD-Client, PHY addresses are not consecutive.*/
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miiphy_write("egiga1", 0xEE, 0xEE, 24);
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#endif
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#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
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defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
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/* configure and initialize both PHY's */
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mv_phy_init("egiga1");
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#endif
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}
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#endif /* CONFIG_RESET_PHY_R */
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