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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
129 lines
2.6 KiB
C
129 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*/
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/*
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* This file provides the interrupt handling functionality for systems
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* based on the standard PC/AT architecture using two cascaded i8259
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* Programmable Interrupt Controllers.
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/ibmpc.h>
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#include <asm/interrupt.h>
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int i8259_init(void)
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{
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u8 i;
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/* Mask all interrupts */
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outb(0xff, MASTER_PIC + IMR);
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outb(0xff, SLAVE_PIC + IMR);
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/*
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* Master PIC
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* Place master PIC interrupts at INT20
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*/
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outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
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outb(0x20, MASTER_PIC + ICW2);
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outb(IR2, MASTER_PIC + ICW3);
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outb(ICW4_PM, MASTER_PIC + ICW4);
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for (i = 0; i < 8; i++)
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outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
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/*
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* Slave PIC
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* Place slave PIC interrupts at INT28
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*/
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outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
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outb(0x28, SLAVE_PIC + ICW2);
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outb(0x02, SLAVE_PIC + ICW3);
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outb(ICW4_PM, SLAVE_PIC + ICW4);
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for (i = 0; i < 8; i++)
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outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
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/*
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* Enable cascaded interrupts by unmasking the cascade IRQ pin of
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* the master PIC
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*/
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unmask_irq(2);
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/* Interrupt 9 should be level triggered (SCI). The OS might do this */
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configure_irq_trigger(9, true);
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return 0;
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}
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void mask_irq(int irq)
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{
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int imr_port;
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if (irq >= SYS_NUM_IRQS)
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return;
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if (irq > 7)
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imr_port = SLAVE_PIC + IMR;
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else
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imr_port = MASTER_PIC + IMR;
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outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
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}
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void unmask_irq(int irq)
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{
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int imr_port;
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if (irq >= SYS_NUM_IRQS)
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return;
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if (irq > 7)
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imr_port = SLAVE_PIC + IMR;
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else
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imr_port = MASTER_PIC + IMR;
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outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
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}
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void specific_eoi(int irq)
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{
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if (irq >= SYS_NUM_IRQS)
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return;
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if (irq > 7) {
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/*
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* IRQ is on the slave - Issue a corresponding EOI to the
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* slave PIC and an EOI for IRQ2 (the cascade interrupt)
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* on the master PIC
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*/
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outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
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irq = SEOI_IR2;
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}
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outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
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}
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void configure_irq_trigger(int int_num, bool is_level_triggered)
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{
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u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
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debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
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if (is_level_triggered)
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int_bits |= (1 << int_num);
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else
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int_bits &= ~(1 << int_num);
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/* Write new values */
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debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
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outb((u8)(int_bits & 0xff), ELCR1);
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outb((u8)(int_bits >> 8), ELCR2);
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}
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