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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
3.2 KiB
C
150 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <pci.h>
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#include <qfw.h>
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#include <dm/platdata.h>
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#include <asm/irq.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/device.h>
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#include <asm/arch/qemu.h>
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static bool i440fx;
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#if CONFIG_IS_ENABLED(QFW_PIO)
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U_BOOT_DRVINFO(x86_qfw_pio) = {
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.name = "qfw_pio",
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};
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#endif
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static void enable_pm_piix(void)
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{
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u8 en;
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u16 cmd;
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/* Set the PM I/O base */
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pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
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/* Enable access to the PM I/O space */
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pci_read_config16(PIIX_PM, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_IO;
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pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
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/* PM I/O Space Enable (PMIOSE) */
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pci_read_config8(PIIX_PM, PMREGMISC, &en);
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en |= PMIOSE;
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pci_write_config8(PIIX_PM, PMREGMISC, en);
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}
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static void enable_pm_ich9(void)
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{
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/* Set the PM I/O base */
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pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
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}
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void qemu_chipset_init(void)
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{
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u16 device, xbcs;
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int pam, i;
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/*
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* i440FX and Q35 chipset have different PAM register offset, but with
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* the same bitfield layout. Here we determine the offset based on its
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* PCI device ID.
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*/
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pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
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i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
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pam = i440fx ? I440FX_PAM : Q35_PAM;
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/*
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* Initialize Programmable Attribute Map (PAM) Registers
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*
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* Configure legacy segments C/D/E/F to system RAM
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*/
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for (i = 0; i < PAM_NUM; i++)
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pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
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if (i440fx) {
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/*
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* Enable legacy IDE I/O ports decode
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*
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* Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
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* However Linux ata_piix driver does sanity check on these two
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* registers to see whether legacy ports decode is turned on.
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* This is to make Linux ata_piix driver happy.
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*/
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pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
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pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
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/* Enable I/O APIC */
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pci_read_config16(PIIX_ISA, XBCS, &xbcs);
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xbcs |= APIC_EN;
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pci_write_config16(PIIX_ISA, XBCS, xbcs);
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enable_pm_piix();
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} else {
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/* Configure PCIe ECAM base address */
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pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
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CONFIG_PCIE_ECAM_BASE | BAR_EN);
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enable_pm_ich9();
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}
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}
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#if CONFIG_IS_ENABLED(X86_32BIT_INIT)
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int checkcpu(void)
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{
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return 0;
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}
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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#endif
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int arch_early_init_r(void)
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{
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qemu_chipset_init();
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return 0;
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}
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#ifdef CONFIG_GENERATE_MP_TABLE
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int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
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{
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u8 irq;
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if (i440fx) {
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/*
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* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
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* connected to I/O APIC INTPIN#16-19. Instead they are routed
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* to an irq number controled by the PIRQ routing register.
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*/
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pci_read_config8(PCI_BDF(bus, dev, func),
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PCI_INTERRUPT_LINE, &irq);
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} else {
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/*
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* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
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* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
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*/
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irq = pirq < 8 ? pirq + 16 : pirq + 12;
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}
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return irq;
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}
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#endif
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