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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/cpu_common.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/pci.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/uart.h>
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#include <power/acpi_pmc.h>
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/* Define this here to avoid referencing any drivers for the debug UART 1 */
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#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
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void cpu_flush_l1d_to_l2(void)
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{
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struct msr_t msr;
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msr = msr_read(MSR_POWER_MISC);
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msr.lo |= FLUSH_DL1_L2;
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msr_write(MSR_POWER_MISC, msr);
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}
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void enable_pm_timer_emulation(const struct udevice *pmc)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
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msr_t msr;
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/*
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* The derived frequency is calculated as follows:
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* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
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*
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* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
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* used.
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*/
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msr.hi = (3579545ULL << 32) / CTC_FREQ;
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/* Set PM1 timer IO port and enable */
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msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
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debug("PM timer %x %x\n", msr.hi, msr.lo);
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msr_write(MSR_EMULATE_PM_TIMER, msr);
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}
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static void pch_uart_init(void)
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{
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/*
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* Set up the pinmux so that the UART rx/tx signals are connected
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* outside the SoC.
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*
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* There are about 500 lines of code required to program the GPIO
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* configuration for the UARTs. But it boils down to four writes, and
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* for the debug UART we want the minimum possible amount of code before
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* the UART is running. So just add the magic writes here. See
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* apl_hostbridge_early_init_pinctrl() for the full horror.
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*/
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if (PCI_FUNC(PCH_DEV_UART) == 1) {
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writel(0x40000402, 0xd0c50650);
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writel(0x3c47, 0xd0c50654);
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writel(0x40000400, 0xd0c50658);
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writel(0x3c48, 0xd0c5065c);
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} else { /* UART2 */
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writel(0x40000402, 0xd0c50670);
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writel(0x3c4b, 0xd0c50674);
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writel(0x40000400, 0xd0c50678);
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writel(0x3c4c, 0xd0c5067c);
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}
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#ifdef CONFIG_DEBUG_UART
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apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE));
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#endif
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}
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static void p2sb_enable_bar(ulong bar)
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{
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/* Enable PCR Base address in PCH */
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pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
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PCI_SIZE_32);
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pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
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/* Enable P2SB MSE */
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pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
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PCI_SIZE_8);
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}
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/*
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* board_debug_uart_init() - Init the debug UART ready for use
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*
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* This is the minimum init needed to get the UART running. It avoids any
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* drivers or complex code, so that the UART is running as soon as possible.
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*/
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void board_debug_uart_init(void)
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{
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p2sb_enable_bar(IOMAP_P2SB_BAR);
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pch_uart_init();
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}
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