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40c76dfed2
The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
48 lines
968 B
C
48 lines
968 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 SiFive, Inc
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*/
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#include <cache.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#ifndef CONFIG_SPL_BUILD
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void enable_caches(void)
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{
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struct udevice *dev;
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int ret;
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/* Enable ways of ccache */
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ret = uclass_get_device_by_driver(UCLASS_CACHE,
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DM_DRIVER_GET(sifive_ccache),
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&dev);
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if (ret) {
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log_debug("Cannot enable cache ways");
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} else {
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ret = cache_enable(dev);
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if (ret)
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log_debug("ccache enable failed");
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}
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}
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#else
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static inline void probe_cache_device(struct driver *driver, struct udevice *dev)
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{
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for (uclass_find_first_device(UCLASS_CACHE, &dev);
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dev;
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uclass_find_next_device(&dev)) {
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if (dev->driver == driver)
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device_probe(dev);
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}
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}
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void enable_caches(void)
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{
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struct udevice *dev = NULL;
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probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
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}
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#endif /* !CONFIG_SPL_BUILD */
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