Leo Yu-Chi Liang 1d29c718b7 andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND ... Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND to do cache flush operation in M-mode and S-mode. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2024-05-30 16:01:13 +08:00
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andes	andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND	2024-05-30 16:01:13 +08:00
cv1800b	riscv: cache: Implement dcache for cv1800b	2024-04-09 11:30:02 +08:00
fu540	board: sifive: Rename spl_soc_init() to spl_dram_init()	2024-05-02 00:01:18 +08:00
fu740	board: sifive: Rename spl_soc_init() to spl_dram_init()	2024-05-02 00:01:18 +08:00
generic	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00
jh7110	board: starfive: Rename spl_soc_init() to spl_dram_init()	2024-05-02 00:01:18 +08:00
cpu.c	riscv: support extension probing using riscv, isa-extensions	2024-04-09 11:30:17 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Align the trap handler to 64 bytes	2023-11-02 15:15:46 +08:00
start.S	riscv: remove cache enablement in start.S	2024-05-30 16:01:09 +08:00
u-boot-spl.lds	riscv: Update alignment for some sections in linker scripts	2023-04-20 20:45:08 +08:00
u-boot.lds	riscv: Fix alignment of RELA sections in the linker scripts	2023-06-27 10:09:51 +08:00