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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
125 lines
2.4 KiB
C
125 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_SERDES_H
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#define __FSL_SERDES_H
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#include <config.h>
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enum srds_prtcl {
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/*
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* Nobody will check whether the device 'NONE' has been configured,
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* So use it to indicate if the serdes_prtcl_map has been initialized.
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*/
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NONE = 0,
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PCIE1,
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PCIE2,
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PCIE3,
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PCIE4,
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SATA1,
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SATA2,
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SRIO1,
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SRIO2,
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SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC10,
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SGMII_FM2_DTSEC1,
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4,
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SGMII_FM2_DTSEC5,
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SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC10,
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SGMII_TSEC1,
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SGMII_TSEC2,
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SGMII_TSEC3,
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SGMII_TSEC4,
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XAUI_FM1,
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XAUI_FM2,
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AURORA,
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CPRI1,
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CPRI2,
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CPRI3,
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CPRI4,
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CPRI5,
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CPRI6,
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CPRI7,
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CPRI8,
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XAUI_FM1_MAC9,
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XAUI_FM1_MAC10,
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XAUI_FM2_MAC9,
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XAUI_FM2_MAC10,
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HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10,
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HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10,
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QSGMII_FM1_A, /* A indicates MACs 1-4 */
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QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
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QSGMII_FM2_A,
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QSGMII_FM2_B,
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XFI_FM1_MAC1,
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XFI_FM1_MAC2,
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XFI_FM1_MAC9,
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XFI_FM1_MAC10,
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XFI_FM2_MAC9,
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XFI_FM2_MAC10,
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INTERLAKEN,
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QSGMII_SW1_A, /* Indicates ports on L2 Switch */
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QSGMII_SW1_B,
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SGMII_2500_FM1_DTSEC1,
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SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC3,
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SGMII_2500_FM1_DTSEC4,
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SGMII_2500_FM1_DTSEC5,
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SGMII_2500_FM1_DTSEC6,
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SGMII_2500_FM1_DTSEC9,
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SGMII_2500_FM1_DTSEC10,
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SGMII_2500_FM2_DTSEC1,
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SGMII_2500_FM2_DTSEC2,
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SGMII_2500_FM2_DTSEC3,
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SGMII_2500_FM2_DTSEC4,
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SGMII_2500_FM2_DTSEC5,
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SGMII_2500_FM2_DTSEC6,
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SGMII_2500_FM2_DTSEC9,
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SGMII_2500_FM2_DTSEC10,
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SGMII_SW1_MAC1,
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SGMII_SW1_MAC2,
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SGMII_SW1_MAC3,
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SGMII_SW1_MAC4,
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SGMII_SW1_MAC5,
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SGMII_SW1_MAC6,
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SERDES_PRCTL_COUNT /* Keep this item the last one */
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};
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enum srds {
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FSL_SRDS_1 = 0,
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FSL_SRDS_2 = 1,
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FSL_SRDS_3 = 2,
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FSL_SRDS_4 = 3,
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};
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int is_serdes_configured(enum srds_prtcl device);
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void fsl_serdes_init(void);
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const char *serdes_clock_to_string(u32 clock);
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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#else
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int serdes_get_first_lane(enum srds_prtcl device);
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
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void serdes_reset_rx(enum srds_prtcl device);
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#endif
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#endif
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#endif /* __FSL_SERDES_H */
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