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https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
142 lines
3.3 KiB
C
142 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
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* Copyright (C) 1995, 1996 Paul M. Antoine
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* Copyright (C) 1998 Ulf Carlsson
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2014, Imagination Technologies Ltd.
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*/
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#include <asm/global_data.h>
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#include <asm/ptrace.h>
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#include <config.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/system.h>
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#include <asm/u-boot.h>
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DECLARE_GLOBAL_DATA_PTR;
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static unsigned long saved_ebase;
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static void show_regs(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int cause = regs->cp0_cause;
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unsigned int exccode;
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int i;
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/*
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* Saved main processor registers
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*/
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for (i = 0; i < 32; ) {
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if ((i % 4) == 0)
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printf("$%2d :", i);
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if (i == 0)
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printf(" %0*lx", field, 0UL);
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else if (i == 26 || i == 27)
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printf(" %*s", field, "");
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else
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printf(" %0*lx", field, regs->regs[i]);
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i++;
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if ((i % 4) == 0)
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puts("\n");
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}
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printf("Hi : %0*lx\n", field, regs->hi);
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printf("Lo : %0*lx\n", field, regs->lo);
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/*
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* Saved cp0 registers
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*/
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printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
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field, regs->cp0_epc - gd->reloc_off);
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printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
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field, regs->regs[31] - gd->reloc_off);
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printf("Status: %08x\n", (uint32_t) regs->cp0_status);
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exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
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printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
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if (1 <= exccode && exccode <= 5)
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printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
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printf("PrId : %08x\n", read_c0_prid());
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}
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void do_reserved(const struct pt_regs *regs)
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{
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puts("\nOoops:\n");
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show_regs(regs);
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hang();
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}
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void do_ejtag_debug(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned long depc;
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unsigned int debug;
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depc = read_c0_depc();
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debug = read_c0_debug();
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printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
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field, depc, debug);
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}
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static void set_handler(unsigned long offset, void *addr, unsigned long size)
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{
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unsigned long ebase = gd->irq_sp;
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memcpy((void *)(ebase + offset), addr, size);
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flush_cache(ebase + offset, size);
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}
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static void trap_init(ulong reloc_addr)
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{
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unsigned long ebase = gd->irq_sp;
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set_handler(0x180, &except_vec3_generic, 0x80);
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set_handler(0x280, &except_vec_ejtag_debug, 0x80);
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saved_ebase = read_c0_ebase() & 0xfffff000;
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/* Set WG bit on Octeon to enable writing to bits 63:30 */
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if (IS_ENABLED(CONFIG_ARCH_OCTEON))
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ebase |= MIPS_EBASE_WG;
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write_c0_ebase(ebase);
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clear_c0_status(ST0_BEV);
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execution_hazard_barrier();
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}
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void trap_restore(void)
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{
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set_c0_status(ST0_BEV);
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execution_hazard_barrier();
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#ifdef CONFIG_OVERRIDE_EXCEPTION_VECTOR_BASE
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write_c0_ebase(CONFIG_NEW_EXCEPTION_VECTOR_BASE & 0xfffff000);
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#else
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write_c0_ebase(saved_ebase);
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#endif
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clear_c0_status(ST0_BEV);
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execution_hazard_barrier();
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}
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int arch_initr_trap(void)
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{
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trap_init(CFG_SYS_SDRAM_BASE);
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return 0;
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}
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