mirror of
https://github.com/u-boot/u-boot.git
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d678a59d2d
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commitc8ffd1356d, reversing changes made to2ee6f3a5f7. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
426 lines
13 KiB
C
426 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/handoff_soc64.h>
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#include <asm/arch/system_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static void cm_write_bypass_mainpll(u32 val)
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{
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writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);
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cm_wait_for_fsm();
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}
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static void cm_write_bypass_perpll(u32 val)
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{
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writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static void cm_write_ctrl(u32 val)
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{
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writel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);
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cm_wait_for_fsm();
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*/
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void cm_basic_init(const struct cm_config * const cfg)
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{
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u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;
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if (cfg == 0)
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return;
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/* Put all plls in bypass */
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cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
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cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
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/* setup main PLL dividers where calculate the vcocalib value */
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mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
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CLKMGR_FDBCK_MDIV_MASK;
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refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
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CLKMGR_PLLGLOB_REFCLKDIV_MASK;
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mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
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hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
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CLKMGR_HSCNT_CONST;
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vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
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((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
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CLKMGR_VCOCALIB_MSCNT_OFFSET);
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writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
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~CLKMGR_PLLGLOB_RST_MASK),
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
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writel(cfg->main_pll_fdbck,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
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writel(vcocalib,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);
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writel(cfg->main_pll_pllc0,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);
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writel(cfg->main_pll_pllc1,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);
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writel(cfg->main_pll_nocdiv,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);
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/* setup peripheral PLL dividers */
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/* calculate the vcocalib value */
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mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &
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CLKMGR_FDBCK_MDIV_MASK;
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refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
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CLKMGR_PLLGLOB_REFCLKDIV_MASK;
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mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;
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hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -
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CLKMGR_HSCNT_CONST;
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vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
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((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
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CLKMGR_VCOCALIB_MSCNT_OFFSET);
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writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
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~CLKMGR_PLLGLOB_RST_MASK),
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
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writel(cfg->per_pll_fdbck,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
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writel(vcocalib,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);
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writel(cfg->per_pll_pllc0,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);
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writel(cfg->per_pll_pllc1,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);
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writel(cfg->per_pll_emacctl,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);
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writel(cfg->per_pll_gpiodiv,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);
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/* Take both PLL out of reset and power up */
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setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,
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CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
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#define LOCKED_MASK \
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(CLKMGR_STAT_MAINPLL_LOCKED | \
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CLKMGR_STAT_PERPLL_LOCKED)
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cm_wait_for_lock(LOCKED_MASK);
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/*
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* Dividers for C2 to C9 only init after PLLs are lock. As dividers
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* only take effect upon value change, we shall set a maximum value as
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* default value.
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*/
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
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writel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
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writel(cfg->main_pll_mpuclk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);
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writel(cfg->main_pll_nocclk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);
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writel(cfg->main_pll_cntr2clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);
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writel(cfg->main_pll_cntr3clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);
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writel(cfg->main_pll_cntr4clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);
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writel(cfg->main_pll_cntr5clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);
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writel(cfg->main_pll_cntr6clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);
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writel(cfg->main_pll_cntr7clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);
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writel(cfg->main_pll_cntr8clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);
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writel(cfg->main_pll_cntr9clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);
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writel(cfg->per_pll_cntr2clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);
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writel(cfg->per_pll_cntr3clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);
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writel(cfg->per_pll_cntr4clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);
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writel(cfg->per_pll_cntr5clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);
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writel(cfg->per_pll_cntr6clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);
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writel(cfg->per_pll_cntr7clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);
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writel(cfg->per_pll_cntr8clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);
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writel(cfg->per_pll_cntr9clk,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);
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/* Take all PLLs out of bypass */
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cm_write_bypass_mainpll(0);
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cm_write_bypass_perpll(0);
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/* clear safe mode / out of boot mode */
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cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &
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~(CLKMGR_CTRL_SAFEMODE));
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/* Now ungate non-hw-managed clocks */
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writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);
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writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);
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/* Clear the loss of lock bits (write 1 to clear) */
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writel(CLKMGR_INTER_PERPLLLOST_MASK |
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CLKMGR_INTER_MAINPLLLOST_MASK,
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socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);
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}
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static unsigned long cm_get_main_vco_clk_hz(void)
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{
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unsigned long fref, refdiv, mdiv, reg, vco;
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reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);
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fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
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CLKMGR_PLLGLOB_VCO_PSRC_MASK;
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switch (fref) {
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case CLKMGR_VCO_PSRC_EOSC1:
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fref = cm_get_osc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_INTOSC:
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fref = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_F2S:
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fref = cm_get_fpga_clk_hz();
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break;
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}
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refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
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CLKMGR_PLLGLOB_REFCLKDIV_MASK;
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reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);
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mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
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vco = fref / refdiv;
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vco = vco * (CLKMGR_MDIV_CONST + mdiv);
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return vco;
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}
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static unsigned long cm_get_per_vco_clk_hz(void)
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{
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unsigned long fref, refdiv, mdiv, reg, vco;
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reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);
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fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
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CLKMGR_PLLGLOB_VCO_PSRC_MASK;
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switch (fref) {
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case CLKMGR_VCO_PSRC_EOSC1:
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fref = cm_get_osc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_INTOSC:
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fref = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_F2S:
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fref = cm_get_fpga_clk_hz();
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break;
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}
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refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
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CLKMGR_PLLGLOB_REFCLKDIV_MASK;
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reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);
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mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
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vco = fref / refdiv;
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vco = vco * (CLKMGR_MDIV_CONST + mdiv);
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return vco;
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}
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unsigned long cm_get_mpu_clk_hz(void)
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{
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unsigned long clock = readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_MPUCLK);
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clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
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switch (clock) {
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case CLKMGR_CLKSRC_MAIN:
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clock = cm_get_main_vco_clk_hz();
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clock /= (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_PLLC0) &
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CLKMGR_PLLC0_DIV_MASK);
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break;
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case CLKMGR_CLKSRC_PER:
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clock = cm_get_per_vco_clk_hz();
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clock /= (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_PERPLL_PLLC0) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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}
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clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);
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return clock;
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}
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unsigned int cm_get_l3_main_clk_hz(void)
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{
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u32 clock = readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_NOCCLK);
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clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
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switch (clock) {
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case CLKMGR_CLKSRC_MAIN:
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clock = cm_get_main_vco_clk_hz();
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clock /= (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_PLLC1) &
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CLKMGR_PLLC0_DIV_MASK);
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break;
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case CLKMGR_CLKSRC_PER:
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clock = cm_get_per_vco_clk_hz();
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clock /= (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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}
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clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);
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return clock;
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}
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unsigned int cm_get_mmc_controller_clk_hz(void)
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{
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u32 clock = readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_PERPLL_CNTR6CLK);
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clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
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switch (clock) {
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case CLKMGR_CLKSRC_MAIN:
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clock = cm_get_l3_main_clk_hz();
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clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_CNTR6CLK) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_PER:
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clock = cm_get_l3_main_clk_hz();
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clock /= 1 + (readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_PERPLL_CNTR6CLK) &
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CLKMGR_CLKCNT_MSK);
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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}
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return clock / 4;
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}
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unsigned int cm_get_l4_sp_clk_hz(void)
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{
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u32 clock = cm_get_l3_main_clk_hz();
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clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
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CLKMGR_S10_MAINPLL_NOCDIV) >>
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CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
|
|
return clock;
|
|
}
|
|
|
|
unsigned int cm_get_spi_controller_clk_hz(void)
|
|
{
|
|
u32 clock = cm_get_l3_main_clk_hz();
|
|
|
|
clock /= (1 << ((readl(socfpga_get_clkmgr_addr() +
|
|
CLKMGR_S10_MAINPLL_NOCDIV) >>
|
|
CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
|
|
return clock;
|
|
}
|
|
|
|
unsigned int cm_get_l4_sys_free_clk_hz(void)
|
|
{
|
|
return cm_get_l3_main_clk_hz() / 4;
|
|
}
|
|
|
|
/*
|
|
* Override weak dw_spi_get_clk implementation in designware_spi.c driver
|
|
*/
|
|
|
|
int dw_spi_get_clk(struct udevice *bus, ulong *rate)
|
|
{
|
|
*rate = cm_get_spi_controller_clk_hz();
|
|
if (!*rate) {
|
|
printf("SPI: clock rate is zero");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cm_print_clock_quick_summary(void)
|
|
{
|
|
printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
|
|
printf("L3 main %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
|
|
printf("Main VCO %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
|
|
printf("Per VCO %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
|
|
printf("EOSC1 %d kHz\n", cm_get_osc_clk_hz() / 1000);
|
|
printf("HPS MMC %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
|
|
printf("UART %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
|
|
}
|