Caleb Connolly 69e9b3428b serial: msm: calculate bit clock divider ... The driver currently requires the bit clock divider be hardcoded in devicetree (or use the hardcoded default from apq8016). The bit clock divider is used to derive the baud rate from the core clock: baudrate = clk_rate / csr_div clk_rate is the actual programmed core clock rate which is returned by clk_set_rate(), and this UART driver only supports a baudrate of 115200. We can therefore determine the appropriate value for UARTDM_CSR by iterating over the possible values and finding the one where the equation above holds true for a baudrate of 115200. Implement this logic and drop the non-standard DT bindings for this driver. Tested on dragonboard410c. Tested-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>		2024-04-23 13:29:16 +02:00
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8250.txt
altera_jtaguart.txt
altera_uart.txt
bcm2835-aux-uart.txt
mcf-uart.txt
microchip,pic32-uart.txt
msm-geni-serial.txt	serial: msm-geni: Use upstream Linux bindings	2023-05-02 14:23:58 -04:00
mxc-serial.txt
omap_serial.txt
pl01x.txt
qca,ar9330-uart.txt
sandbox-serial.txt
sh.txt	serial: sh: Add HSCIF support for R-Car SoC	2023-04-07 17:13:28 +02:00
snps-dw-apb-uart.txt
xilinx_uartlite.txt