u-boot/arch/riscv/cpu
Simon Glass bef9fdbed2 arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11 11:44:47 -06:00
..
andes andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND 2024-05-30 16:01:13 +08:00
ast2700 riscv: Add AST2700 SoC initial platform support 2024-09-11 20:35:03 +08:00
cv1800b riscv: cache: Implement dcache for cv1800b 2024-04-09 11:30:02 +08:00
fu540 arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11 11:44:47 -06:00
fu740 arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11 11:44:47 -06:00
generic riscv: Remove common.h usage 2023-10-24 16:34:45 -04:00
jh7110 arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11 11:44:47 -06:00
cpu.c riscv: support extension probing using riscv, isa-extensions 2024-04-09 11:30:17 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Align the trap handler to 64 bytes 2023-11-02 15:15:46 +08:00
start.S arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11 11:44:47 -06:00
u-boot-spl.lds riscv: u-boot-spl.lds: Remove _image_binary_end alignment 2024-09-11 20:35:03 +08:00
u-boot.lds riscv: Fix alignment of RELA sections in the linker scripts 2023-06-27 10:09:51 +08:00