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04ea9147d5
Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng <tingting.meng@altera.com>
136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#define MAX_IO96B_SUPPORTED 2
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#define MAX_MEM_INTERFACE_SUPPORTED 2
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#define NUM_CMD_RESPONSE_DATA 3
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#define NUM_CMD_PARAM 7
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/* supported mailbox command type */
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enum iossm_mailbox_cmd_type {
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CMD_NOP,
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CMD_GET_SYS_INFO,
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CMD_GET_MEM_INFO,
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CMD_GET_MEM_CAL_INFO,
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CMD_TRIG_CONTROLLER_OP,
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CMD_TRIG_MEM_CAL_OP
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};
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/* supported mailbox command opcode */
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enum iossm_mailbox_cmd_opcode {
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ECC_ENABLE_SET = 0x0101,
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ECC_INTERRUPT_MASK = 0x0105,
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ECC_WRITEBACK_ENABLE = 0x0106,
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ECC_INJECT_ERROR = 0x0109,
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ECC_SCRUB_MODE_0_START = 0x0202,
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ECC_SCRUB_MODE_1_START = 0x0203,
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BIST_STANDARD_MODE_START = 0x0301,
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BIST_MEM_INIT_START = 0x0303,
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BIST_SET_DATA_PATTERN_UPPER = 0x0305,
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BIST_SET_DATA_PATTERN_LOWER = 0x0306,
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TRIG_MEM_CAL = 0x000a
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};
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/*
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* IOSSM mailbox required information
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*
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* @num_mem_interface: Number of memory interfaces instantiated
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* @ip_type: IP type implemented on the IO96B
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* @ip_instance_id: IP identifier for every IP instance implemented on the IO96B
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*/
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struct io96b_mb_ctrl {
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u32 num_mem_interface;
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u32 ip_type[2];
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u32 ip_id[2];
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};
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/* CMD_REQ Register Definition */
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#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29)
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#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24)
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#define CMD_TYPE_MASK GENMASK(23, 16)
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#define CMD_OPCODE_MASK GENMASK(15, 0)
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/*
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* IOSSM mailbox request
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* @ip_type: IP type for the specified memory interface
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* @ip_id: IP instance ID for the specified memory interface
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* @usr_cmd_type: User desire IOSSM mailbox command type
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* @usr_cmd_opcode: User desire IOSSM mailbox command opcode
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* @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command
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*/
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struct io96b_mb_req {
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u32 ip_type;
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u32 ip_id;
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u32 usr_cmd_type;
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u32 usr_cmd_opcode;
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u32 cmd_param[NUM_CMD_PARAM];
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};
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/*
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* IOSSM mailbox response outputs
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*
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* @cmd_resp_status: Command Interface status
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* @cmd_resp_data_*: More spaces for command response
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*/
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struct io96b_mb_resp {
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u32 cmd_resp_status;
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u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA];
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};
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/*
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* IO96B instance specific information
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*
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* @size: Memory size
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* @io96b_csr_addr: IO96B instance CSR address
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* @cal_status: IO96B instance calibration status
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* @mb_ctrl: IOSSM mailbox required information
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*/
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struct io96b_instance {
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u16 size;
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phys_addr_t io96b_csr_addr;
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bool cal_status;
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struct io96b_mb_ctrl mb_ctrl;
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};
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/*
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* Overall IO96B instance(s) information
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*
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* @num_instance: Number of instance(s) assigned to HPS
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* @overall_cal_status: Overall calibration status for all IO96B instance(s)
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* @ddr_type: DDR memory type
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* @ecc_status: ECC enable status (false = disabled, true = enabled)
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* @overall_size: Total DDR memory size
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* @io96b[]: IO96B instance specific information
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* @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked)
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* @num_port: Number of IO96B port.
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* @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected,
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* bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected,
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* bit 3: EMIF1 PLL B selected
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*/
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struct io96b_info {
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u8 num_instance;
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bool overall_cal_status;
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const char *ddr_type;
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bool ecc_status;
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u16 overall_size;
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struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
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bool ckgen_lock;
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u8 num_port;
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u8 io96b_pll;
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};
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int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
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u32 resp_data_len, struct io96b_mb_resp *resp);
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/* Supported IOSSM mailbox function */
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void io96b_mb_init(struct io96b_info *io96b_ctrl);
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int io96b_cal_status(phys_addr_t addr);
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void init_mem_cal(struct io96b_info *io96b_ctrl);
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int get_mem_technology(struct io96b_info *io96b_ctrl);
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int get_mem_width_info(struct io96b_info *io96b_ctrl);
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int ecc_enable_status(struct io96b_info *io96b_ctrl);
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int bist_mem_init_start(struct io96b_info *io96b_ctrl);
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bool ecc_interrupt_status(struct io96b_info *io96b_ctrl);
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