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2e9b3014df
With DM clock support in place, it is easy to add RMII support into the MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz. The board DT requires the following adjustments to EQoS node: phy-mode = "rmii"; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_50M>; assigned-clock-rates = <0>, <100000000>, <50000000>; Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
249 lines
5.9 KiB
C
249 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2022 NXP
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <errno.h>
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#include <eth_phy.h>
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#include <log.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <phy.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/arch/clock.h>
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#include <asm/cache.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/mach-imx/sys_proto.h>
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#include <linux/delay.h>
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#include "dwc_eth_qos.h"
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__weak u32 imx_get_eqos_csr_clk(void)
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{
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return 100 * 1000000;
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}
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static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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return clk_get_rate(&eqos->clk_master_bus);
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}
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static int eqos_probe_resources_imx(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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phy_interface_t interface;
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int ret;
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debug("%s(dev=%p):\n", __func__, dev);
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interface = eqos->config->interface(dev);
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if (interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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return -EINVAL;
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}
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eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
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ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
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if (ret) {
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dev_dbg(dev, "clk_get_by_name(master_bus) failed: %d", ret);
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goto err_probe;
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}
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ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
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if (ret) {
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dev_dbg(dev, "clk_get_by_name(ptp_ref) failed: %d", ret);
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goto err_free_clk_master_bus;
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}
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ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
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if (ret) {
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dev_dbg(dev, "clk_get_by_name(tx) failed: %d", ret);
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goto err_free_clk_ptp_ref;
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}
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ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck);
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if (ret) {
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dev_dbg(dev, "clk_get_by_name(pclk) failed: %d", ret);
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goto err_free_clk_tx;
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}
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debug("%s: OK\n", __func__);
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return 0;
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err_free_clk_tx:
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clk_free(&eqos->clk_tx);
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err_free_clk_ptp_ref:
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clk_free(&eqos->clk_ptp_ref);
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err_free_clk_master_bus:
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clk_free(&eqos->clk_master_bus);
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err_probe:
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debug("%s: returns %d\n", __func__, ret);
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return ret;
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}
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static int eqos_remove_resources_imx(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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debug("%s(dev=%p):\n", __func__, dev);
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clk_free(&eqos->clk_ck);
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clk_free(&eqos->clk_tx);
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clk_free(&eqos->clk_ptp_ref);
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clk_free(&eqos->clk_master_bus);
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debug("%s: OK\n", __func__);
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return 0;
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}
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static int eqos_start_clks_imx(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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int ret;
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debug("%s(dev=%p):\n", __func__, dev);
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ret = clk_enable(&eqos->clk_master_bus);
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if (ret < 0) {
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dev_dbg(dev, "clk_enable(clk_master_bus) failed: %d", ret);
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goto err;
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}
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ret = clk_enable(&eqos->clk_ptp_ref);
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if (ret < 0) {
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dev_dbg(dev, "clk_enable(clk_ptp_ref) failed: %d", ret);
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goto err_disable_clk_master_bus;
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}
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ret = clk_enable(&eqos->clk_tx);
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if (ret < 0) {
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dev_dbg(dev, "clk_enable(clk_tx) failed: %d", ret);
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goto err_disable_clk_ptp_ref;
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}
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ret = clk_enable(&eqos->clk_ck);
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if (ret < 0) {
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dev_dbg(dev, "clk_enable(clk_ck) failed: %d", ret);
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goto err_disable_clk_tx;
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}
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debug("%s: OK\n", __func__);
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return 0;
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err_disable_clk_tx:
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clk_disable(&eqos->clk_tx);
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err_disable_clk_ptp_ref:
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clk_disable(&eqos->clk_ptp_ref);
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err_disable_clk_master_bus:
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clk_disable(&eqos->clk_master_bus);
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err:
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debug("%s: FAILED: %d\n", __func__, ret);
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return ret;
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}
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static int eqos_stop_clks_imx(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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debug("%s(dev=%p):\n", __func__, dev);
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clk_disable(&eqos->clk_ck);
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clk_disable(&eqos->clk_tx);
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clk_disable(&eqos->clk_ptp_ref);
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clk_disable(&eqos->clk_master_bus);
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debug("%s: OK\n", __func__);
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return 0;
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}
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static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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ulong rate;
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int ret;
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debug("%s(dev=%p):\n", __func__, dev);
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if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
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rate = 5000; /* 5000 kHz = 5 MHz */
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else
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rate = 2500; /* 2500 kHz = 2.5 MHz */
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if (eqos->phy->speed == SPEED_1000 &&
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(eqos->phy->interface == PHY_INTERFACE_MODE_RGMII ||
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eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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rate *= 50; /* Use 50x base rate i.e. 125 MHz */
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} else if (eqos->phy->speed == SPEED_100) {
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rate *= 10; /* Use 10x base rate */
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} else if (eqos->phy->speed == SPEED_10) {
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rate *= 1; /* Use base rate */
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} else {
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pr_err("invalid speed %d", eqos->phy->speed);
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return -EINVAL;
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}
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rate *= 1000; /* clk_set_rate() operates in Hz */
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ret = clk_set_rate(&eqos->clk_tx, rate);
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if (ret < 0) {
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pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
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return ret;
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}
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return 0;
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}
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static int eqos_get_enetaddr_imx(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
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return 0;
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}
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static struct eqos_ops eqos_imx_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_imx,
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.eqos_remove_resources = eqos_remove_resources_imx,
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.eqos_stop_resets = eqos_null_ops,
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.eqos_start_resets = eqos_null_ops,
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.eqos_stop_clks = eqos_stop_clks_imx,
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.eqos_start_clks = eqos_start_clks_imx,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
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.eqos_get_enetaddr = eqos_get_enetaddr_imx,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
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};
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struct eqos_config __maybe_unused eqos_imx_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 10,
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.swr_wait = 50,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_64,
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.interface = dev_read_phy_mode,
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.ops = &eqos_imx_ops
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};
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