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fd1c2938c0
Instructions such as dcbi are in the X-form; they have RA and RB fields and the effective address (EA) is computed as (RA|0)+(RB). In words, this means that if RA is zero, the left-hand side of the addition is zero, otherwise the corresponding GPR is used. r0 can never be used on the left-hand side of a X-form instruction. For D-form instructions such as addis, the Power ISA illustrates this in the instruction pseudo-code: if RA = 0 then RT <- EXTS(SI || 0x0000) else RT <- (RA) + EXIS(SI || 0x0000) In all of these cases, RA=0 indicates the value zero, not register r0. I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig (MPC85xx) that this patch results in the same machine code. Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
106 lines
2.7 KiB
ArmAsm
106 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
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* Copyright Freescale Semiconductor, Inc. 2004, 2006.
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbf */
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/* Description: Data Cache block flush */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbf
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ppcDcbf:
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dcbf 0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbi */
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/* Description: Data Cache block Invalidate */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbi
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ppcDcbi:
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dcbi 0,r3
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blr
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/*--------------------------------------------------------------------------
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* Function: ppcDcbz
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* Description: Data Cache block zero.
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* Input: r3 = effective address
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* Output: none.
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*-------------------------------------------------------------------------- */
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.globl ppcDcbz
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ppcDcbz:
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dcbz 0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcSync */
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/* Description: Processor Synchronize */
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/* Input: none. */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcSync
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ppcSync:
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sync
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blr
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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#endif
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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sync
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1: dcbi 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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#endif
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blr
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