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1cd239f444
Add basic support for SpacemiT's Banana Pi F3 board. Update the k1.dtsi align with mainline. Note that the device tree files follow the mainline Linux source[1]. Links: https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-dt-v5-8-98263aae83be@gentoo.org/ [1] Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Signed-off-by: Huan Zhou <pericycle.cc@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
459 lines
No EOL
13 KiB
Text
459 lines
No EOL
13 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "SpacemiT K1";
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compatible = "spacemit,k1";
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aliases {
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serial0 = &uart0;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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serial7 = &uart8;
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serial8 = &uart9;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <24000000>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_0>;
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};
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core1 {
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cpu = <&cpu_1>;
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};
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core2 {
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cpu = <&cpu_2>;
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};
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core3 {
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cpu = <&cpu_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_4>;
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};
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core1 {
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cpu = <&cpu_5>;
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};
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core2 {
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cpu = <&cpu_6>;
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};
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core3 {
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cpu = <&cpu_7>;
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};
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};
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};
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cpu_0: cpu@0 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_1: cpu@1 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <1>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_2: cpu@2 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <2>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_3: cpu@3 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <3>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_4: cpu@4 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <4>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu4_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_5: cpu@5 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <5>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu5_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_6: cpu@6 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <6>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu6_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_7: cpu@7 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <7>;
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riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu7_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cluster0_l2_cache: l2-cache0 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <512>;
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cache-unified;
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};
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cluster1_l2_cache: l2-cache1 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <512>;
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cache-unified;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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ranges;
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uart0: serial@d4017000 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017000 0x0 0x100>;
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interrupts = <42>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@d4017100 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017100 0x0 0x100>;
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interrupts = <44>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@d4017200 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017200 0x0 0x100>;
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interrupts = <45>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart4: serial@d4017300 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017300 0x0 0x100>;
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interrupts = <46>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart5: serial@d4017400 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017400 0x0 0x100>;
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interrupts = <47>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart6: serial@d4017500 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017500 0x0 0x100>;
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interrupts = <48>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart7: serial@d4017600 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
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reg = <0x0 0xd4017600 0x0 0x100>;
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interrupts = <49>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart8: serial@d4017700 {
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compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xd4017700 0x0 0x100>;
|
|
interrupts = <50>;
|
|
clock-frequency = <14857000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart9: serial@d4017800 {
|
|
compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xd4017800 0x0 0x100>;
|
|
interrupts = <51>;
|
|
clock-frequency = <14857000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
plic: interrupt-controller@e0000000 {
|
|
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
|
|
reg = <0x0 0xe0000000 0x0 0x4000000>;
|
|
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
|
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
|
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
|
<&cpu3_intc 11>, <&cpu3_intc 9>,
|
|
<&cpu4_intc 11>, <&cpu4_intc 9>,
|
|
<&cpu5_intc 11>, <&cpu5_intc 9>,
|
|
<&cpu6_intc 11>, <&cpu6_intc 9>,
|
|
<&cpu7_intc 11>, <&cpu7_intc 9>;
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
riscv,ndev = <159>;
|
|
};
|
|
|
|
clint: timer@e4000000 {
|
|
compatible = "spacemit,k1-clint", "sifive,clint0";
|
|
reg = <0x0 0xe4000000 0x0 0x10000>;
|
|
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
|
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
|
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
|
<&cpu3_intc 3>, <&cpu3_intc 7>,
|
|
<&cpu4_intc 3>, <&cpu4_intc 7>,
|
|
<&cpu5_intc 3>, <&cpu5_intc 7>,
|
|
<&cpu6_intc 3>, <&cpu6_intc 7>,
|
|
<&cpu7_intc 3>, <&cpu7_intc 7>;
|
|
};
|
|
|
|
sec_uart1: serial@f0612000 {
|
|
compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xf0612000 0x0 0x100>;
|
|
interrupts = <43>;
|
|
clock-frequency = <14857000>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "reserved"; /* for TEE usage */
|
|
};
|
|
};
|
|
}; |