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456ee909d6
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated into the SoC which is enabled by the FSP. Remove the smsc47x superio initialization codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
27 lines
386 B
C
27 lines
386 B
C
/*
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* Copyright (C) 2015, Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <netdev.h>
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int arch_early_init_r(void)
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{
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/* do the pin-muxing */
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gpio_ich6_pinctrl_init();
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return 0;
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}
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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return;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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