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5996a8a835
While testing on some Kirkwood platforms it was noticed that the timer
did not function correctly all the time. The driver did not correctly
handle 32bit timer value wrap arounds. Using the timer_conv_64()
conversion function fixes this issue.
Fixes: e9e73d78a8 ("timer: add orion-timer support")
Suggested-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier-oss@weidmueller.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <asm/io.h>
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#include <common.h>
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#include <dm/device.h>
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#include <dm/fdtaddr.h>
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#include <timer.h>
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#define TIMER_CTRL 0x00
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#define TIMER0_EN BIT(0)
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#define TIMER0_RELOAD_EN BIT(1)
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#define TIMER0_RELOAD 0x10
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#define TIMER0_VAL 0x14
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struct orion_timer_priv {
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void *base;
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};
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static uint64_t orion_timer_get_count(struct udevice *dev)
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{
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struct orion_timer_priv *priv = dev_get_priv(dev);
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return timer_conv_64(~readl(priv->base + TIMER0_VAL));
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}
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static int orion_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct orion_timer_priv *priv = dev_get_priv(dev);
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priv->base = devfdt_remap_addr_index(dev, 0);
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if (!priv->base) {
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debug("unable to map registers\n");
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return -ENOMEM;
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}
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uc_priv->clock_rate = CONFIG_SYS_TCLK;
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writel(~0, priv->base + TIMER0_VAL);
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writel(~0, priv->base + TIMER0_RELOAD);
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/* enable timer */
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setbits_le32(priv->base + TIMER_CTRL, TIMER0_EN | TIMER0_RELOAD_EN);
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return 0;
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}
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static const struct timer_ops orion_timer_ops = {
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.get_count = orion_timer_get_count,
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};
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static const struct udevice_id orion_timer_ids[] = {
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{ .compatible = "marvell,orion-timer" },
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{}
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};
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U_BOOT_DRIVER(orion_timer) = {
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.name = "orion_timer",
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.id = UCLASS_TIMER,
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.of_match = orion_timer_ids,
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.probe = orion_timer_probe,
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.ops = &orion_timer_ops,
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.priv_auto = sizeof(struct orion_timer_priv),
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};
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