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9f5df9a3ef
The different macros use writel which is defined in asm/io.h, so let's include the header so users of hardware.h do not need to include asm/io.h as well. While at it, remove asm/io.h includes wherever asm/arch-rockchip/hardware.h is included already. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
74 lines
1.5 KiB
C
74 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C)Copyright 2016 Rockchip Electronics Co., Ltd
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* Authors: Andy Yan <andy.yan@rock-chips.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <syscon.h>
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#include <asm/global_data.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/grf_rv1108.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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struct rv1108_grf *grf;
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enum {
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GPIO3C3_SHIFT = 6,
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GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
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GPIO3C2_SHIFT = 4,
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GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
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GPIO2D2_SHIFT = 4,
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GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
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GPIO2D2_GPIO = 0,
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GPIO2D2_UART2_SOUT_M0,
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GPIO2D1_SHIFT = 2,
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GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
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GPIO2D1_GPIO = 0,
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GPIO2D1_UART2_SIN_M0,
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};
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/* Elgin board use UART2 m0 for debug*/
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D2_MASK | GPIO2D1_MASK,
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GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
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GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
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rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
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return 0;
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}
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#define MODEM_ENABLE_GPIO 111
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int rk_board_late_init(void)
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{
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gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
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gpio_direction_output(MODEM_ENABLE_GPIO, 0);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = 0x8000000;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = 0x60000000;
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gd->bd->bi_dram[0].size = 0x8000000;
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return 0;
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}
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