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https://github.com/u-boot/u-boot.git
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6d8cdfd153
FIT checksum validation is very slow in SPL due to D-cache not being enabled. Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation, from seconds to milliseconds. This change enables caches in SPL on all Rockchip ARM64 boards, the Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to disable caches for a specific board or SoC if needed. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
155 lines
3.5 KiB
C
155 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_return_to_bootrom(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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return 0;
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}
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__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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};
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const char *board_spl_was_booted_from(void)
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{
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u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
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const char *bootdevice_ofpath = NULL;
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if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
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bootdevice_ofpath = boot_devices[bootdevice_brom_id];
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if (bootdevice_ofpath)
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debug("%s: brom_bootdevice_id %x maps to '%s'\n",
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__func__, bootdevice_brom_id, bootdevice_ofpath);
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else
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debug("%s: failed to resolve brom_bootdevice_id %x\n",
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__func__, bootdevice_brom_id);
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return bootdevice_ofpath;
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}
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u32 spl_boot_device(void)
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{
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u32 boot_device = BOOT_DEVICE_MMC1;
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#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
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defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
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defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
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defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY) || \
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defined(CONFIG_TARGET_CHROMEBOOK_BOB) || \
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defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
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return BOOT_DEVICE_SPI;
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#endif
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if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
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return BOOT_DEVICE_BOOTROM;
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return boot_device;
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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return MMCSD_MODE_RAW;
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}
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#define TIMER_LOAD_COUNT_L 0x00
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#define TIMER_LOAD_COUNT_H 0x04
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_EN 0x1
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#define TIMER_FMODE BIT(0)
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#define TIMER_RMODE BIT(1)
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__weak void rockchip_stimer_init(void)
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{
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#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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if (reg & TIMER_EN)
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return;
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#ifndef CONFIG_ARM64
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(CONFIG_COUNTER_FREQUENCY));
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#endif
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
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writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
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TIMER_CONTROL_REG);
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#endif
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}
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__weak int board_early_init_f(void)
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{
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return 0;
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}
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__weak int arch_cpu_init(void)
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{
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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board_early_init_f();
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ret = spl_early_init();
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if (ret) {
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printf("spl_early_init() failed: %d\n", ret);
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hang();
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}
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arch_cpu_init();
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rockchip_stimer_init();
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#ifdef CONFIG_SYS_ARCH_TIMER
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/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
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timer_init();
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#endif
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#if !defined(CONFIG_TPL) || defined(CONFIG_SPL_RAM)
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debug("\nspl:init dram\n");
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ret = dram_init();
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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return;
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}
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gd->ram_top = gd->ram_base + get_effective_memsize();
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gd->ram_top = board_get_usable_ram_top(gd->ram_size);
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if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
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gd->relocaddr = gd->ram_top;
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arch_reserve_mmu();
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enable_caches();
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}
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#endif
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preloader_console_init();
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}
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void spl_board_prepare_for_boot(void)
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{
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if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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return;
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cleanup_before_linux();
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}
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