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https://github.com/u-boot/u-boot.git
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c60b835be2
Similar to RK35xx the BootRom in RK3328 can read all data and look for idbloader at 0x8000, same as it does for SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/grf_rk3328.h>
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#include <asm/arch-rockchip/uart.h>
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#include <asm/armv8/mmu.h>
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#define CRU_BASE 0xFF440000
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#define GRF_BASE 0xFF100000
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#define UART2_BASE 0xFF130000
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#define FW_DDR_CON_REG 0xFF7C0040
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#define EFUSE_NS_BASE 0xFF260000
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#define EFUSE_MOD 0x0000
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#define EFUSE_INT_CON 0x0014
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#define EFUSE_T_CSB_P 0x0028
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#define EFUSE_T_PGENB_P 0x002C
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#define EFUSE_T_LOAD_P 0x0030
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#define EFUSE_T_ADDR_P 0x0034
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#define EFUSE_T_STROBE_P 0x0038
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#define EFUSE_T_CSB_R 0x003C
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#define EFUSE_T_PGENB_R 0x0040
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#define EFUSE_T_LOAD_R 0x0044
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#define EFUSE_T_ADDR_R 0x0048
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#define EFUSE_T_STROBE_R 0x004C
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#define EFUSE_USER_MODE 0x1
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#define EFUSE_TIMING(s, l) (((s) << 16) | (l))
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
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[BROM_BOOTSOURCE_SPINOR] = "/spi@ff190000/flash@0",
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[BROM_BOOTSOURCE_SD] = "/mmc@ff500000",
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};
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static struct mm_region rk3328_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xff000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xff000000UL,
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.phys = 0xff000000UL,
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.size = 0x1000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3328_mem_map;
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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u32 reg;
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/* We do some SoC one time setting here. */
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/* Disable the ddr secure region setting to make it non-secure */
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rk_setreg(FW_DDR_CON_REG, 0x200);
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/* Use efuse auto mode */
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reg = readl(EFUSE_NS_BASE + EFUSE_MOD);
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writel(reg & ~EFUSE_USER_MODE, EFUSE_NS_BASE + EFUSE_MOD);
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/* Enable efuse finish and auto access err interrupt */
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writel(0x07, EFUSE_NS_BASE + EFUSE_INT_CON);
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/* Set efuse timing control */
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writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_CSB_P);
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writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_PGENB_P);
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writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_LOAD_P);
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writel(EFUSE_TIMING(1, 241), EFUSE_NS_BASE + EFUSE_T_ADDR_P);
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writel(EFUSE_TIMING(2, 240), EFUSE_NS_BASE + EFUSE_T_STROBE_P);
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writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_CSB_R);
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writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_PGENB_R);
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writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_LOAD_R);
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writel(EFUSE_TIMING(1, 4), EFUSE_NS_BASE + EFUSE_T_ADDR_R);
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writel(EFUSE_TIMING(2, 3), EFUSE_NS_BASE + EFUSE_T_STROBE_R);
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#endif
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return 0;
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}
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void board_debug_uart_init(void)
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{
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struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
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struct rk_uart * const uart = (void *)UART2_BASE;
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enum{
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GPIO2A0_SEL_SHIFT = 0,
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GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
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GPIO2A0_UART2_TX_M1 = 1,
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GPIO2A1_SEL_SHIFT = 2,
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GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
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GPIO2A1_UART2_RX_M1 = 1,
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};
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enum {
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IOMUX_SEL_UART2_SHIFT = 0,
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IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
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IOMUX_SEL_UART2_M0 = 0,
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IOMUX_SEL_UART2_M1,
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};
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/* uart_sel_clk default select 24MHz */
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writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
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/* init uart baud rate 1500000 */
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writel(0x83, &uart->lcr);
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writel(0x1, &uart->rbr);
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writel(0x3, &uart->lcr);
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/* Enable early UART2 */
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rk_clrsetreg(&grf->com_iomux,
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IOMUX_SEL_UART2_MASK,
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IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A0_SEL_MASK,
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GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A1_SEL_MASK,
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GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
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/* enable FIFO */
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writel(0x1, &uart->sfe);
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}
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