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u-boot/drivers/usb/eth/asix88179.c
Khoa Hoang 05278af8b3 eth: asix88179: packet drop when receiving large fragmented packets 
The ASIX 88179A drops packets when receiving fragmented packets larger
than the MTU size due to an insufficient URB buffer size. This change
synchronizes the URB buffer size with the configuration used in the
Linux kernel, resolving the packet drop issue.

To reproduce the issue, set the following configuration:
    CONFIG_IP_DEFRAG=y
    CONFIG_TFTP_BLOCKSIZE=16352

Then, run the `tftp` command. It will fail with a timeout error:

    U-Boot> tftp zero.bin
    Using ax88179_eth device
    TFTP from server 10.0.0.196; our IP address is 10.0.0.18
    Filename 'zero.bin'
    Load address: 0x10000000
    Loading: T T T T T T T T T T T
    Retry count exceeded; starting again

Signed-off-by: Khoa Hoang <admin@khoahoang.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-11-25 19:11:19 +01:00

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
* based on the U-Boot Asix driver as well as information
* from the Linux AX88179_178a driver
*/
#include <dm.h>
#include <log.h>
#include <usb.h>
#include <net.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include "usb_ether.h"
#include <malloc.h>
#include <memalign.h>
#include <errno.h>
/* ASIX AX88179 based USB 3.0 Ethernet Devices */
#define AX88179_PHY_ID 0x03
#define AX_EEPROM_LEN 0x100
#define AX88179_EEPROM_MAGIC 0x17900b95
#define AX_MCAST_FLTSIZE 8
#define AX_MAX_MCAST 64
#define AX_INT_PPLS_LINK (1 << 16)
#define AX_RXHDR_L4_TYPE_MASK 0x1c
#define AX_RXHDR_L4_TYPE_UDP 4
#define AX_RXHDR_L4_TYPE_TCP 16
#define AX_RXHDR_L3CSUM_ERR 2
#define AX_RXHDR_L4CSUM_ERR 1
#define AX_RXHDR_CRC_ERR (1 << 29)
#define AX_RXHDR_DROP_ERR (1 << 31)
#define AX_ENDPOINT_INT 0x01
#define AX_ENDPOINT_IN 0x02
#define AX_ENDPOINT_OUT 0x03
#define AX_ACCESS_MAC 0x01
#define AX_ACCESS_PHY 0x02
#define AX_ACCESS_EEPROM 0x04
#define AX_ACCESS_EFUS 0x05
#define AX_PAUSE_WATERLVL_HIGH 0x54
#define AX_PAUSE_WATERLVL_LOW 0x55
#define PHYSICAL_LINK_STATUS 0x02
#define AX_USB_SS (1 << 2)
#define AX_USB_HS (1 << 1)
#define GENERAL_STATUS 0x03
#define AX_SECLD (1 << 2)
#define AX_SROM_ADDR 0x07
#define AX_SROM_CMD 0x0a
#define EEP_RD (1 << 2)
#define EEP_BUSY (1 << 4)
#define AX_SROM_DATA_LOW 0x08
#define AX_SROM_DATA_HIGH 0x09
#define AX_RX_CTL 0x0b
#define AX_RX_CTL_DROPCRCERR (1 << 8)
#define AX_RX_CTL_IPE (1 << 9)
#define AX_RX_CTL_START (1 << 7)
#define AX_RX_CTL_AP (1 << 5)
#define AX_RX_CTL_AM (1 << 4)
#define AX_RX_CTL_AB (1 << 3)
#define AX_RX_CTL_AMALL (1 << 1)
#define AX_RX_CTL_PRO (1 << 0)
#define AX_RX_CTL_STOP 0
#define AX_NODE_ID 0x10
#define AX_MULFLTARY 0x16
#define AX_MEDIUM_STATUS_MODE 0x22
#define AX_MEDIUM_GIGAMODE (1 << 0)
#define AX_MEDIUM_FULL_DUPLEX (1 << 1)
#define AX_MEDIUM_EN_125MHZ (1 << 3)
#define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
#define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
#define AX_MEDIUM_RECEIVE_EN (1 << 8)
#define AX_MEDIUM_PS (1 << 9)
#define AX_MEDIUM_JUMBO_EN 0x8040
#define AX_MONITOR_MOD 0x24
#define AX_MONITOR_MODE_RWLC (1 << 1)
#define AX_MONITOR_MODE_RWMP (1 << 2)
#define AX_MONITOR_MODE_PMEPOL (1 << 5)
#define AX_MONITOR_MODE_PMETYPE (1 << 6)
#define AX_GPIO_CTRL 0x25
#define AX_GPIO_CTRL_GPIO3EN (1 << 7)
#define AX_GPIO_CTRL_GPIO2EN (1 << 6)
#define AX_GPIO_CTRL_GPIO1EN (1 << 5)
#define AX_PHYPWR_RSTCTL 0x26
#define AX_PHYPWR_RSTCTL_BZ (1 << 4)
#define AX_PHYPWR_RSTCTL_IPRL (1 << 5)
#define AX_PHYPWR_RSTCTL_AT (1 << 12)
#define AX_RX_BULKIN_QCTRL 0x2e
#define AX_CLK_SELECT 0x33
#define AX_CLK_SELECT_BCS (1 << 0)
#define AX_CLK_SELECT_ACS (1 << 1)
#define AX_CLK_SELECT_ULR (1 << 3)
#define AX_RXCOE_CTL 0x34
#define AX_RXCOE_IP (1 << 0)
#define AX_RXCOE_TCP (1 << 1)
#define AX_RXCOE_UDP (1 << 2)
#define AX_RXCOE_TCPV6 (1 << 5)
#define AX_RXCOE_UDPV6 (1 << 6)
#define AX_TXCOE_CTL 0x35
#define AX_TXCOE_IP (1 << 0)
#define AX_TXCOE_TCP (1 << 1)
#define AX_TXCOE_UDP (1 << 2)
#define AX_TXCOE_TCPV6 (1 << 5)
#define AX_TXCOE_UDPV6 (1 << 6)
#define AX_LEDCTRL 0x73
#define GMII_PHY_PHYSR 0x11
#define GMII_PHY_PHYSR_SMASK 0xc000
#define GMII_PHY_PHYSR_GIGA (1 << 15)
#define GMII_PHY_PHYSR_100 (1 << 14)
#define GMII_PHY_PHYSR_FULL (1 << 13)
#define GMII_PHY_PHYSR_LINK (1 << 10)
#define GMII_LED_ACT 0x1a
#define GMII_LED_ACTIVE_MASK 0xff8f
#define GMII_LED0_ACTIVE (1 << 4)
#define GMII_LED1_ACTIVE (1 << 5)
#define GMII_LED2_ACTIVE (1 << 6)
#define GMII_LED_LINK 0x1c
#define GMII_LED_LINK_MASK 0xf888
#define GMII_LED0_LINK_10 (1 << 0)
#define GMII_LED0_LINK_100 (1 << 1)
#define GMII_LED0_LINK_1000 (1 << 2)
#define GMII_LED1_LINK_10 (1 << 4)
#define GMII_LED1_LINK_100 (1 << 5)
#define GMII_LED1_LINK_1000 (1 << 6)
#define GMII_LED2_LINK_10 (1 << 8)
#define GMII_LED2_LINK_100 (1 << 9)
#define GMII_LED2_LINK_1000 (1 << 10)
#define LED0_ACTIVE (1 << 0)
#define LED0_LINK_10 (1 << 1)
#define LED0_LINK_100 (1 << 2)
#define LED0_LINK_1000 (1 << 3)
#define LED0_FD (1 << 4)
#define LED0_USB3_MASK 0x001f
#define LED1_ACTIVE (1 << 5)
#define LED1_LINK_10 (1 << 6)
#define LED1_LINK_100 (1 << 7)
#define LED1_LINK_1000 (1 << 8)
#define LED1_FD (1 << 9)
#define LED1_USB3_MASK 0x03e0
#define LED2_ACTIVE (1 << 10)
#define LED2_LINK_1000 (1 << 13)
#define LED2_LINK_100 (1 << 12)
#define LED2_LINK_10 (1 << 11)
#define LED2_FD (1 << 14)
#define LED_VALID (1 << 15)
#define LED2_USB3_MASK 0x7c00
#define GMII_PHYPAGE 0x1e
#define GMII_PHY_PAGE_SELECT 0x1f
#define GMII_PHY_PGSEL_EXT 0x0007
#define GMII_PHY_PGSEL_PAGE0 0x0000
/* local defines */
#define ASIX_BASE_NAME "axg"
#define USB_CTRL_SET_TIMEOUT 5000
#define USB_CTRL_GET_TIMEOUT 5000
#define USB_BULK_SEND_TIMEOUT 5000
#define USB_BULK_RECV_TIMEOUT 5000
#define AX_RX_URB_SIZE 1024 * 0x1a
#define BLK_FRAME_SIZE 0x200
#define PHY_CONNECT_TIMEOUT 5000
#define PHY_RESET_TIMEOUT 500
#define TIMEOUT_RESOLUTION 50 /* ms */
#define FLAG_NONE 0
#define FLAG_TYPE_AX88179 (1U << 0)
#define FLAG_TYPE_AX88178a (1U << 1)
#define FLAG_TYPE_DLINK_DUB1312 (1U << 2)
#define FLAG_TYPE_SITECOM (1U << 3)
#define FLAG_TYPE_SAMSUNG (1U << 4)
#define FLAG_TYPE_LENOVO (1U << 5)
#define FLAG_TYPE_GX3 (1U << 6)
/* local vars */
static const struct {
unsigned char ctrl, timer_l, timer_h, size, ifg;
} AX88179_BULKIN_SIZE[] = {
{7, 0x4f, 0, 0x12, 0xff},
{7, 0x20, 3, 0x16, 0xff},
{7, 0xae, 7, 0x18, 0xff},
{7, 0xcc, 0x4c, 0x18, 8},
};
/* driver private */
struct asix_private {
struct ueth_data ueth;
unsigned pkt_cnt;
uint8_t *pkt_data;
uint32_t *pkt_hdr;
int flags;
int rx_urb_size;
int maxpacketsize;
};
/*
* Asix infrastructure commands
*/
static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
u16 size, void *data)
{
int len;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
cmd, value, index, size);
memcpy(buf, data, size);
len = usb_control_msg(
dev->pusb_dev,
usb_sndctrlpipe(dev->pusb_dev, 0),
cmd,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
value,
index,
buf,
size,
USB_CTRL_SET_TIMEOUT);
return len == size ? 0 : ECOMM;
}
static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
u16 size, void *data)
{
int len;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
cmd, value, index, size);
len = usb_control_msg(
dev->pusb_dev,
usb_rcvctrlpipe(dev->pusb_dev, 0),
cmd,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
value,
index,
buf,
size,
USB_CTRL_GET_TIMEOUT);
memcpy(data, buf, size);
return len == size ? 0 : ECOMM;
}
static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr)
{
int ret;
ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr);
if (ret < 0)
debug("Failed to read MAC address: %02x\n", ret);
return ret;
}
static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr)
{
int ret;
ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
ETH_ALEN, enetaddr);
if (ret < 0)
debug("Failed to set MAC address: %02x\n", ret);
return ret;
}
static int asix_reset_phy(struct ueth_data *dev)
{
u16 bmcr;
u32 t;
/* Reset the PHY */
bmcr = BMCR_RESET;
asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
for (t = 0; t < PHY_RESET_TIMEOUT; t += TIMEOUT_RESOLUTION) {
asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
if (!(bmcr & BMCR_RESET))
return 0;
mdelay(TIMEOUT_RESOLUTION);
}
debug("Reset PHY timeout\n");
return -ETIMEDOUT;
}
static int asix_basic_reset(struct ueth_data *dev,
struct asix_private *dev_priv)
{
u8 buf[5];
u16 *tmp16;
u8 *tmp;
tmp16 = (u16 *)buf;
tmp = (u8 *)buf;
/* Power up ethernet PHY */
*tmp16 = 0;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
*tmp16 = AX_PHYPWR_RSTCTL_IPRL;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
mdelay(200);
*tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
mdelay(200);
/* RX bulk configuration */
memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
dev_priv->rx_urb_size = 1024 * 20;
/* Water Level configuration */
*tmp = 0x34;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
*tmp = 0x52;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
/* Enable checksum offload */
*tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
*tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
/* Configure RX control register => start operation */
*tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
*tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
AX_MONITOR_MODE_RWMP;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
/* Configure default medium type => giga */
*tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
asix_reset_phy(dev);
u16 adv = 0;
adv = ADVERTISE_ALL | ADVERTISE_CSMA |
ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
adv = ADVERTISE_1000FULL;
asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
/* Restart auto-negotiation */
u16 bmcr = 0;
asix_read_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_BMCR, 2, &bmcr);
return 0;
}
static int asix_wait_link(struct ueth_data *dev)
{
int timeout = 0;
int link_detected;
u8 buf[2];
u16 *tmp16;
tmp16 = (u16 *)buf;
do {
asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
MII_BMSR, 2, buf);
link_detected = *tmp16 & BMSR_LSTATUS;
if (!link_detected) {
if (timeout == 0)
printf("Waiting for Ethernet connection... ");
mdelay(TIMEOUT_RESOLUTION);
timeout += TIMEOUT_RESOLUTION;
}
} while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
if (link_detected) {
if (timeout > 0)
printf("done.\n");
return 0;
} else {
printf("unable to connect.\n");
return -ENETUNREACH;
}
}
static int asix_init_common(struct ueth_data *dev,
struct asix_private *dev_priv)
{
u8 buf[2], tmp[5], link_sts;
u16 *tmp16, mode;
tmp16 = (u16 *)buf;
debug("** %s()\n", __func__);
/* Configure RX control register => start operation */
*tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
goto out_err;
if (asix_wait_link(dev) != 0) {
/*reset device and try again*/
printf("Reset Ethernet Device\n");
asix_basic_reset(dev, dev_priv);
if (asix_wait_link(dev) != 0)
goto out_err;
}
/* Configure link */
mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
AX_MEDIUM_RXFLOW_CTRLEN;
asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
1, 1, &link_sts);
asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
GMII_PHY_PHYSR, 2, tmp16);
if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
return 0;
} else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
AX_MEDIUM_JUMBO_EN;
if (link_sts & AX_USB_SS)
memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
else if (link_sts & AX_USB_HS)
memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
else
memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
} else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
mode |= AX_MEDIUM_PS;
if (link_sts & (AX_USB_SS | AX_USB_HS))
memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
else
memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
} else {
memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
}
/* RX bulk configuration */
asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
if (*tmp16 & GMII_PHY_PHYSR_FULL)
mode |= AX_MEDIUM_FULL_DUPLEX;
asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
2, 2, &mode);
return 0;
out_err:
return -1;
}
static int asix_send_common(struct ueth_data *dev,
struct asix_private *dev_priv,
void *packet, int length)
{
int err;
u32 packet_len, tx_hdr2;
int actual_len, framesize;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
PKTSIZE + (2 * sizeof(packet_len)));
debug("** %s(), len %d\n", __func__, length);
packet_len = length;
cpu_to_le32s(&packet_len);
memcpy(msg, &packet_len, sizeof(packet_len));
framesize = dev_priv->maxpacketsize;
tx_hdr2 = 0;
if (((length + 8) % framesize) == 0)
tx_hdr2 |= 0x80008000; /* Enable padding */
cpu_to_le32s(&tx_hdr2);
memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
(void *)packet, length);
err = usb_bulk_msg(dev->pusb_dev,
usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
(void *)msg,
length + sizeof(packet_len) + sizeof(tx_hdr2),
&actual_len,
USB_BULK_SEND_TIMEOUT);
debug("Tx: len = %zu, actual = %u, err = %d\n",
length + sizeof(packet_len), actual_len, err);
return err;
}
static int ax88179_eth_start(struct udevice *dev)
{
struct asix_private *priv = dev_get_priv(dev);
return asix_init_common(&priv->ueth, priv);
}
void ax88179_eth_stop(struct udevice *dev)
{
struct asix_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
debug("** %s()\n", __func__);
usb_ether_advance_rxbuf(ueth, -1);
priv->pkt_cnt = 0;
priv->pkt_data = NULL;
priv->pkt_hdr = NULL;
}
int ax88179_eth_send(struct udevice *dev, void *packet, int length)
{
struct asix_private *priv = dev_get_priv(dev);
return asix_send_common(&priv->ueth, priv, packet, length);
}
int ax88179_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct asix_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
int ret, len;
u16 pkt_len;
/* No packet left, get a new one */
if (priv->pkt_cnt == 0) {
uint8_t *ptr;
u16 pkt_cnt;
u16 hdr_off;
u32 rx_hdr;
len = usb_ether_get_rx_bytes(ueth, &ptr);
debug("%s: first try, len=%d\n", __func__, len);
if (!len) {
if (!(flags & ETH_RECV_CHECK_DEVICE))
return -EAGAIN;
ret = usb_ether_receive(ueth, priv->rx_urb_size);
if (ret < 0)
return ret;
len = usb_ether_get_rx_bytes(ueth, &ptr);
debug("%s: second try, len=%d\n", __func__, len);
}
if (len < 4) {
usb_ether_advance_rxbuf(ueth, -1);
return -EMSGSIZE;
}
rx_hdr = *(u32 *)(ptr + len - 4);
le32_to_cpus(&rx_hdr);
pkt_cnt = (u16)rx_hdr;
if (pkt_cnt == 0) {
usb_ether_advance_rxbuf(ueth, -1);
return 0;
}
hdr_off = (u16)(rx_hdr >> 16);
if (hdr_off > len - 4) {
usb_ether_advance_rxbuf(ueth, -1);
return -EIO;
}
priv->pkt_cnt = pkt_cnt;
priv->pkt_data = ptr;
priv->pkt_hdr = (u32 *)(ptr + hdr_off);
debug("%s: %d packets received, pkt header at %d\n",
__func__, (int)priv->pkt_cnt, (int)hdr_off);
}
le32_to_cpus(priv->pkt_hdr);
pkt_len = (*priv->pkt_hdr >> 16) & 0x1fff;
*packetp = priv->pkt_data + 2;
priv->pkt_data += (pkt_len + 7) & 0xFFF8;
priv->pkt_cnt--;
priv->pkt_hdr++;
debug("%s: return packet of %d bytes (%d packets left)\n",
__func__, (int)pkt_len, priv->pkt_cnt);
return pkt_len;
}
static int ax88179_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
{
struct asix_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
if (priv->pkt_cnt == 0)
usb_ether_advance_rxbuf(ueth, -1);
return 0;
}
int ax88179_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
struct ueth_data *ueth = &priv->ueth;
return asix_write_mac(ueth, pdata->enetaddr);
}
static int ax88179_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct asix_private *priv = dev_get_priv(dev);
struct usb_device *usb_dev;
int ret;
priv->flags = dev->driver_data;
ret = usb_ether_register(dev, &priv->ueth, AX_RX_URB_SIZE);
if (ret)
return ret;
usb_dev = priv->ueth.pusb_dev;
priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT];
ret = asix_basic_reset(&priv->ueth, priv);
if (ret) {
printf("Failed to reset ethernet device\n");
return ret;
}
/* Get the MAC address */
ret = asix_read_mac(&priv->ueth, pdata->enetaddr);
if (ret)
return ret;
debug("MAC %pM\n", pdata->enetaddr);
return 0;
}
static const struct eth_ops ax88179_eth_ops = {
.start = ax88179_eth_start,
.send = ax88179_eth_send,
.recv = ax88179_eth_recv,
.free_pkt = ax88179_free_pkt,
.stop = ax88179_eth_stop,
.write_hwaddr = ax88179_write_hwaddr,
};
U_BOOT_DRIVER(ax88179_eth) = {
.name = "ax88179_eth",
.id = UCLASS_ETH,
.probe = ax88179_eth_probe,
.ops = &ax88179_eth_ops,
.priv_auto = sizeof(struct asix_private),
.plat_auto = sizeof(struct eth_pdata),
};
static const struct usb_device_id ax88179_eth_id_table[] = {
{ USB_DEVICE(0x0b95, 0x1790), .driver_info = FLAG_TYPE_AX88179 },
{ USB_DEVICE(0x0b95, 0x178a), .driver_info = FLAG_TYPE_AX88178a },
{ USB_DEVICE(0x2001, 0x4a00), .driver_info = FLAG_TYPE_DLINK_DUB1312 },
{ USB_DEVICE(0x0df6, 0x0072), .driver_info = FLAG_TYPE_SITECOM },
{ USB_DEVICE(0x04e8, 0xa100), .driver_info = FLAG_TYPE_SAMSUNG },
{ USB_DEVICE(0x17ef, 0x304b), .driver_info = FLAG_TYPE_LENOVO },
{ USB_DEVICE(0x04b4, 0x3610), .driver_info = FLAG_TYPE_GX3 },
{ } /* Terminating entry */
};
U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table);
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