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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <cpu_func.h>
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#include <asm/cache.h>
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#include <watchdog.h>
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static ulong maybe_watchdog_reset(ulong flushed)
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{
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flushed += CONFIG_SYS_CACHELINE_SIZE;
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if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
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schedule();
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flushed = 0;
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}
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return flushed;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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ulong addr, start, end;
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ulong flushed = 0;
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start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
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end = start_addr + size - 1;
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for (addr = start; (addr <= end) && (addr >= start);
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addr += CONFIG_SYS_CACHELINE_SIZE) {
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asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
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flushed = maybe_watchdog_reset(flushed);
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}
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/* wait for all dcbst to complete on bus */
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asm volatile("sync" : : : "memory");
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for (addr = start; (addr <= end) && (addr >= start);
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addr += CONFIG_SYS_CACHELINE_SIZE) {
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asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
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flushed = maybe_watchdog_reset(flushed);
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}
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asm volatile("sync" : : : "memory");
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/* flush prefetch queue */
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asm volatile("isync" : : : "memory");
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}
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