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00a7767766
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the rest of the ddr/marvell/a38x code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
100 lines
3.4 KiB
C
100 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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/* Design Guidelines parameters */
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u32 g_zpri_data = 123; /* controller data - P drive strength */
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u32 g_znri_data = 123; /* controller data - N drive strength */
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u32 g_zpri_ctrl = 74; /* controller C/A - P drive strength */
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u32 g_znri_ctrl = 74; /* controller C/A - N drive strength */
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u32 g_zpodt_data = 45; /* controller data - P ODT */
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u32 g_znodt_data = 45; /* controller data - N ODT */
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u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
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u32 g_znodt_ctrl = 45; /* controller data - N ODT */
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u32 g_odt_config_2cs = 0x120012;
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u32 g_odt_config_1cs = 0x10000;
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u32 g_rtt_nom = 0x44;
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u32 g_dic = 0x2;
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/*
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* Configure phy (called by static init controller) for static flow
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*/
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int ddr3_tip_configure_phy(u32 dev_num)
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{
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u32 if_id, phy_id;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
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PAD_ZRI_CALIB_PHY_REG,
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((0x7f & g_zpri_data) << 7 | (0x7f & g_znri_data))));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
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PAD_ZRI_CALIB_PHY_REG,
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((0x7f & g_zpri_ctrl) << 7 | (0x7f & g_znri_ctrl))));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
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PAD_ODT_CALIB_PHY_REG,
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((0x3f & g_zpodt_data) << 6 | (0x3f & g_znodt_data))));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
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PAD_ODT_CALIB_PHY_REG,
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((0x3f & g_zpodt_ctrl) << 6 | (0x3f & g_znodt_ctrl))));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
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PAD_PRE_DISABLE_PHY_REG, 0));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
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CMOS_CONFIG_PHY_REG, 0));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
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CMOS_CONFIG_PHY_REG, 0));
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for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
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/* check if the interface is enabled */
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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for (phy_id = 0;
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phy_id < tm->num_of_bus_per_interface;
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phy_id++) {
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VALIDATE_ACTIVE(tm->bus_act_mask, phy_id);
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/* Vref & clamp */
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CHECK_STATUS(ddr3_tip_bus_read_modify_write
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(dev_num, ACCESS_TYPE_UNICAST,
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if_id, phy_id, DDR_PHY_DATA,
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PAD_CONFIG_PHY_REG,
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((clamp_tbl[if_id] << 4) | vref),
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((0x7 << 4) | 0x7)));
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/* clamp not relevant for control */
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CHECK_STATUS(ddr3_tip_bus_read_modify_write
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(dev_num, ACCESS_TYPE_UNICAST,
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if_id, phy_id, DDR_PHY_CONTROL,
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PAD_CONFIG_PHY_REG, 0x4, 0x7));
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}
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}
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0x90,
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0x6002));
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return MV_OK;
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}
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